Phase Locked Loop For Radiation Hardened Environment

This thesis describes a Phase Locked Loop (PLL) design for operation within a radiation environment. Specific design architecture and techniques were implemented to help mitigate radiation effects that degrade PLL performance. This thesis presents several elements of a rad-hard PLL that were developed to solve this challenge, such as a very wideband coupling coefficient LC VCO that has a much higher frequency tuning range than conventional varactor based LC VCOs. The PLL consists a Phase and Frequency Detector (PFD), a rail to rail charge pump, a loop filter, the quadrature LC tank Voltage Controlled Oscillator (VCO), a Current Mode Logic (CML) frequency divider, a True Single-Phase Clocked (TSPC) divider, and a Differential to Single-ended converter (D2S). The main radiation effects on MOSFETs include changes of threshold voltage and mobility, which causes the drain current to decrease. As a result, the phase noise and tuning range of PLL are degraded. The proposed radiation hard PLL uses the unique Peregrine Semiconductor Corp (PSC) 0.25um Silicon on Sapphire (SOS) CMOS process technology. The center frequency is 3.6 GHz, and the tuning range is from 2.3 GHz to 5.1 GHz. The minimum frequency tuning range is 70% under pre-radiation and post-radiation conditions. Simulated power consumption is 124.23 mW in pre-radiation and 145.73 mW in post-radiation. Simulated pre-radiation phase noise is -130 dBc/Hz at 1 MHz offset, and post-radiation phase noise is -127.9 dBc/Hz at 1MHz offset. The locking time is less than 450ns under post-radiation conditions. The overall focus is on a systematic design methodology for radiation-hardened PLL in a SOS CMOS process.