Browsing by Subject "wideband"
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Item A wideband frequency synthesizer for built-in self testing of analog integrated circuits(Texas A&M University, 2004-11-15) Yan, WenjianThe cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). The frequency generator or frequency synthesizer is a key element of the BIST. It generates the clock frequencies needed for testing. A wide-band frequency synthesizer is designed in the project. The architecture of a PLL is analyzed as well as the modifications carried out. The modified structure has three blocks: basic PLL based frequency synthesizer, frequency down-converter, and output selector. Each of these blocks is analyzed and designed. This frequency synthesizer system overcomes challenges faced by the traditional PLL based frequency synthesizer.Item Digitally-Assisted Mixed-Signal Wideband Compressive Sensing(2012-07-16) Yu, ZhuizhuanDigitizing wideband signals requires very demanding analog-to-digital conversion (ADC) speed and resolution specifications. In this dissertation, a mixed-signal parallel compressive sensing system is proposed to realize the sensing of wideband sparse signals at sub-Nqyuist rate by exploiting the signal sparsity. The mixed-signal compressive sensing is realized with a parallel segmented compressive sensing (PSCS) front-end, which not only can filter out the harmonic spurs that leak from the local random generator, but also provides a tradeoff between the sampling rate and the system complexity such that a practical hardware implementation is possible. Moreover, the signal randomization in the system is able to spread the spurious energy due to ADC nonlinearity along the signal bandwidth rather than concentrate on a few frequencies as it is the case for a conventional ADC. This important new property relaxes the ADC SFDR requirement when sensing frequency-domain sparse signals. The mixed-signal compressive sensing system performance is greatly impacted by the accuracy of analog circuit components, especially with the scaling of CMOS technology. In this dissertation, the effect of the circuit imperfection in the mixed-signal compressive sensing system based on the PSCS front-end is investigated in detail, such as the finite settling time, the timing uncertainty and so on. An iterative background calibration algorithm based on LMS (Least Mean Square) is proposed, which is shown to be able to effectively calibrate the error due to the circuit nonideal factors. A low-speed prototype built with off-the-shelf components is presented. The prototype is able to sense sparse analog signals with up to 4 percent sparsity at 32 percent of the Nqyuist rate. Many practical constraints that arose during building the prototype such as circuit nonidealities are addressed in detail, which provides good insights for a future high-frequency integrated circuit implementation. Based on that, a high-frequency sub-Nyquist rate receiver exploiting the parallel compressive sensing is designed and fabricated with IBM90nm CMOS technology, and measurement results are presented to show the capability of wideband compressive sensing at sub-Nyquist rate. To the best of our knowledge, this prototype is the first reported integrated chip for wideband mixed-signal compressive sensing. The proposed prototype achieves 7 bits ENOB and 3 GS/s equivalent sampling rate in simulation assuming a 0.5 ps state-of-art jitter variance, whose FOM beats the FOM of the high speed state-of-the-art Nyquist ADCs by 2-3 times. The proposed mixed-signal compressive sensing system can be applied in various fields. In particular, its applications for wideband spectrum sensing for cognitive radios and spectrum analysis in RF tests are discussed in this work.Item Frequency Synthesizers and Oscillator Architectures Based on Multi-Order Harmonic Generation(2012-02-14) Abdul-Latif, MohammedFrequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply.Item Power Supply Rejection Improvement Techniques In Low Drop-Out Voltage Regulators(2011-10-21) Ganta, SaikrishnaLow drop out (LDO) voltage regulators are widely used for post regulating the switching ripples generated by the switched mode power supplies (SMPS). Due to demand for portable applications, industry is pushing for complete system on chip power management solutions. Hence, the switching frequencies of the SMPS are increasing to allow higher level of integration. Therefore, the subsequent post-regulator LDO must have good power supply rejection (PSR) up to switching frequencies of SMPS. Unfortunately, the conventional LDOs have poor PSR at high frequencies. The objective of this research is to develop novel LDO regulators that can achieve good high frequency PSR performance. In this thesis, two PSR improvement methods are presented. The first method proposes a novel power supply noise-cancelling scheme to improve the PSR of an external-capacitor LDO. The proposed power supply noise-cancelling scheme is designed using adaptive power consumption, thereby not degrading the power efficiency of the LDO. The second method proposes a feed forward ripple cancellation technique to improve the PSR of capacitor-less LDO; also a dynamically powered transient improvement scheme has been proposed. The feed forward ripple cancellation is designed by reusing the load transient improvement block, thus achieving the improvement in PSR with no additional power consumption. Both the projects have been designed in TSMC 0.18 ?m technology. The first method achieves a PSR of 66 dB up to 1 MHz where as the second method achieves a 55 dB PSR up to 1 MHz.Item Wideband dual-linear polarized microstrip patch antenna(2009-05-15) Smith, Christopher BrianDue to the recent interest in broadband antennas a microstrip patch antenna was developed to meet the need for a cheap, low profile, broadband antenna. This antenna could be used in a wide range of applications such as in the communications industry for cell phones or satellite communication. Particle Swarm Optimization was used to design the dual-linear polarization broadband microstrip antenna and impedance matching network. This optimization method greatly reduced the time needed to find viable antenna parameters. A dual input patch antenna with over 30% bandwidth in the X-band was simulated using Ansoft's High Frequency Structural Simulator (HFSS) in conjunction with Particle Swarm Optimization. A single input and a dual input antenna was then fabricated. The fabricated antennas were composed of stacked microstrip patches over a set of bowtie apertures in the ground plane that were perpendicular to one another. A dual offset microstrip feedline was used to feed the aperture. Two different layers were used for the microstrip feedline of each polarization. The resulting measured impedance bandwidth was even wider than predicted. The antenna pattern was measured at several frequencies over the antenna bandwidth and was found to have good gain, consistent antenna patterns and low cross polarization.