Browsing by Subject "folding"
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Item Computational Study of the Development of Graphene Based Devices(2012-02-14) Bellido Sosa, EdsonGraphene is a promising material for many technological applications. To realize these applications, new fabrication techniques that allow precise control of the physical properties, as well as large scale integration between single devices are needed. In this work, a series of studies are performed in order to develop graphene based devices. First, using MD simulations we study the effects of irradiating graphene with a carbon ion atom at several positions and energies from 0.1 eV to 100 keV. The simulations show four types of processes adsorption, reflection, transmission, and vacancy formation. At energies below 10 eV the dominant process is reflection, between 10 and 100 eV is adsorption, and between 100 eV and 100 keV the dominant process is transmission. Vacancy formation is a low rate process that takes place at energies above 30 eV. Three types of defects were found: adatom, single vacancy, and 5-8-5 defect formed from a double vacancy defect. Also a bottom-up fabrication method is studied, in this method, the controlled folding of graphene structures, driven by molecular interactions with water nanodroplets, is analyzed considering the interactions with substrates such as SiO2, HMDS and IPA on SiO2. When the graphene is supported on SiO2, the attraction between graphene and the substrate prevents graphene from folding but if the substrate has HMDS or IPA, the interaction between graphene and the substrate is weak, and depending on the geometry of the graphene structure, folding is possible. Finally, to evaluate the characteristics of graphene based devices, we model the vibrational bending modes of graphene ribbons with different dimensions. The resonant frequencies of the ribbons and relations between the size of the ribbon and their resonant frequencies are calculated. The interaction of a graphene vibronic device with water and IPA molecules are simulated and demonstrate that this device can be used as a sensitive vibronic molecular sensor that is able to distinguish the chemical nature of the detected molecule. Also, the electrical properties of the graphene vibronic with armchair and zigzag border are calculated; the latter has the potential to generate THz electrical signals as demonstrated in this work.Item Design of high speed folding and interpolating analog-to-digital converter(Texas A&M University, 2004-09-30) Li, YunchuHigh-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F&I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F&I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35?m CMOS process to verify the ideas. The S/H and F&I ADC prototype is realized in 0.35?m double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.