Browsing by Subject "UHV"
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Item Design and Construction of a Low Temperature Scanning Tunneling Microscope(2010-10-12) Chen, ChiA low temperature scanning tunneling microscope (LTSTM) was built that we could use in an ultra high vacuum (UHV) system. The scanning tunneling microscope (STM) was tested on an existing 3He cryostat and calibrated at room, liquid nitrogen and helium temperatures. We analyzed the operational electronic and vibration noises and made some effective improvements. To demonstrate the capabilities of the STM, we obtained atomically resolved images of the Au (111) and graphite surfaces. In addition, we showed that the stable tunneling junctions can be formed between the Pt/Ir tip and a superconducting thin film PbBi. We observed the atomic corrugation on Au (111) and measured the height of the atomic steps to be approximately2.53?, which agrees with published values. In our images of the graphite surface, we found both the ? atoms triangular structure, as well as the complete ?-? hexagonal unit cell, using the same tip and the same bias voltage of 0.2V. The successful observation of the hidden ? atoms of graphite is encouraging in regards to the possibility of imaging other materials with atomic resolution using our STM. We also demonstrated that stable tunneling junctions can be formed at various temperatures. To demonstrate this, the superconducting current-voltage and differential conductance-voltage characteristics of a PbBi film were measured from 1.1K to 9K From this data, the temperature dependent energy gap of the superconductor was shown to be consistent with the predictions of the Bardeen, Cooper, and Schrieffer (BCS) theory.Item Epitaxial germanium via Ge:C and its use in non-classical semiconductor devices(2015-12) Mantey, Jason Christopher; Banerjee, Sanjay; Lee, Jack C; Register, Leonard F; Akinwande, Deji; Ferreira, Paulo JThe microelectronics industry has been using Silicon (Si) as the primary material for complementary metal-oxide-semiconductor (CMOS) chip fabrication for more than six decades. Throughout this time, these CMOS devices have gotten exponentially smaller, faster, and cheaper. While new materials and fabrication processes have been slowly added over the years, the CMOS device of today is largely the same as it was decades ago. However, field-effect transistors (FETs) have now scaled so far that Si is approaching physical limits. Thus, new channel materials and new fundamental device structures are being investigated to replace traditional CMOS. Germanium is one of the prime candidates to replace Si in the FET channel, with its increased electron and hole mobilities compared to Si. Perhaps more importantly, it is compatible with the existing Si manufacturing techniques by epitaxially growing thin layers of Ge crystal on the starting Si wafer. Because these two crystals do not share a lattice constant, there will inevitably be crystal defects in the thin Ge layer that can be catastrophic for device functionality. Several approaches have been introduced to reduce defects, but most of them are wastefully thick (>1 um) or require complex manufacturing methods. In this work, we utilize an extremely thin (~10 nm) buffer layer of carbon-doped Ge (Ge:C) to grow Ge and SiGe layers for FET and virtual substrate applications with improved crystalline quality and reduced surface roughnesses. These thin Ge layers not only offer new pathways for MOSFETs, but can also be used in non-classical structures. Semiconductor nanowires (NWs) and tunnel-FETs (TFETs) are two of the most promising device architectures, and both can be used with Ge. This dissertation presents a simulated Si/Ge heterostructure interface TFET that can be fabricated on a virtual substrate made with the Ge:C buffer layer. Detailed analysis on device operation is given. Also in this work is the fabrication process for individually addressable Ge NW-FETs. The NWs offer excellent electrostatic gate control through reduced dimensions and offer another potential pathway for Ge in a post-CMOS world.