Browsing by Subject "Transmitter"
Now showing 1 - 3 of 3
Results Per Page
Sort Options
Item Design of a Direct-Modulation Transmitter with Self-Optimizing Feedback and a Highly Linear, Highly Reconfigurable, Continuously-Tunable Active-RC Baseband Filter for Multiple Standards(2012-02-14) Amir Aslanzadeh Mamaghani, HesamThis work consists of two main parts: i) Design and implementation of a compact current-reusing 2.4GHz direct-modulation transmitter with on-chip automatic tuning; ii) Design and implementation of a novel highly-reconfigurable, continuously tunable, power-adjustable Active-RC filter for multiple standards. The design, analysis, and experimental verification of a proposed self-calibrating, current reused 2.4GHz, direct-modulation transmitter are introduced. A stacked arrangement of the power amplifier/voltage-controlled oscillator is presented along with a novel LC-tank-tuning algorithm with a simple, low-cost, on-chip implementation. To transmit maximum power, the tuning loop ensures the PA's resonant tank is centered around the operating frequency, and the loop requires no ADC, DSP, or external signal generator. This work also details the proposed tuning-loop algorithm and examines the frequency-dependent nonlinear power-detector. The system was implemented in TSMC 0.18[mu]m CMOS, occupies 0.7 mm? (TX) + 0.1 mm? (self tuning), and was measured in a QFN48 package on FR4 PCB. Automatically adjusting the tank-tuning bits within their tuning range results in >4dB increase in output power. With the self-tuning circuit active, the transmitter delivers a measured output power of > 0dBm to a 100-[omega] differential load, and the system consumes 22.9 mA from a 2.2-V supply. A biquad design methodology and a baseband low-pass filter is presented for wireless and wireline applications with reconfigurable frequency response, selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1MHz-20MHz) and adjustable power consumption (3mW-7.5mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel Continuous Impedance Multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and Inverse Chebyshev approximation types. Also, a new stability metric for biquads, Minimum Acceptable Phase Margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3dBm, a THD of -40dB at 447mV[subscript pk, diff] input signal amplitude, and a DR of 71.4dB. The filters tunable range covers frequencies from 1MHz to 20MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than ?2:5%. The design is fabricated in 0.13[mu]m CMOS, occupies 1.53mm?, and operates from a 1-V supply.Item High performance pulse width modulated CMOS class D power amplifiers(2012-12) Lu, Jingxue; Gharpurey, RanjitThe objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation.Item Millimeter-Wave Concurrent Dual-Band BiCMOS RFIC Transmitter for Radar and Communication Systems(2012-11-21) Huynh, Cuong Phu Minh 1976-This dissertation presents new circuit architectures and techniques for improving the performance of several key BiCMOS RFIC building blocks used in radar and wireless communication systems operating up to millimeter-wave frequencies, and the development of an advanced, low-cost and miniature millimeter-wave concurrent dual-band transmitter for short-range, high-resolution radar and high-rate communication systems. A new type of low-power active balun consisting of a common emitter amplifier with degenerative inductor and a common collector amplifier is proposed. The parasitic neutralization and compensation techniques are used to keep the balun well balanced at very high frequencies and across an ultra-wide bandwidth. A novel RF switch architecture with ultra-high isolation and possible gain is proposed, analyzed and demonstrated. The new RF switch architecture achieves an ultra-high isolation through implementation of a new RF leaking cancellation technique. A new class of concurrent dual-band impedance matching networks and technique for synthesizing them are presented together with a 25.5/37-GHz concurrent dual-band PA. These matching networks enable simultaneous matching of two arbitrary loads to two arbitrary sources at two different frequencies, utilizing the impedance-equivalence properties of LC networks that any LC network can be equivalent to an inductor, capacitor, open or short at different frequencies. K- and Ka-band ultra-low-leakage RF-pulse formers capable of producing very narrow RF pulses in the order of 200 ps with small rising and falling time for short-range high-resolution radar and high-data-rate communication systems are also developed. The complete transmitter exhibiting unique characteristics obtained from capabilities of producing very narrow and tunable RF pulses with extremely RF leakage and working concurrently in dual bands at 24.5 and 35 GHz was designed. Capability of generating narrow and tunable RF pulses allows the radar system to flexibly work at high and multiple range resolutions. The extremely low RF leakage allows the transmitter to share one antenna system with receiver, turn on the PA at all time, comply the transmitting spectrum requirements, increase the system dynamic range, avoid harming to other systems; hence improving system size, cost and performance. High data-rate in communication systems is achieved as the consequence of transmitting very narrow RF pulses at high rates. In addition, the dissertation demonstrates a design approach for low chip-area, cost and power consumption systems in which a single dual-band component (power amplifier) is designed to operate with two RF signals simultaneously.