Browsing by Subject "Transimpedance Amplifier"
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Item High performance CMOS integrated circuits for optical receivers(2009-05-15) SamadiBoroujeni, MohammadRezaOptical communications is expanding into new applications such as infrared wireless communications; therefore, designing high performance circuits has gained considerable importance. In this dissertation a wide dynamic-range variable-gain transimpedance amplifier (TIA) is introduced. It adopts a regulated cascode (RGC) amplifier and an operational transconductance amplifier (OTA) as the feed forward gain element to control gain and improve the overload of the optical receiver. A fully-differential variable-gain TIA in a 0.35?m CMOS technology is realized. It provides a bit error rate (BER) less than 10-12 for an input current from 6?A-3mA at 3.3V power supply. For the transimpedance gain variation, from 0.1k?? to 3k??, -3dB bandwidth is higher than 1.7GHz for a 0.6pF photodiode capacitance. The power dissipations for the highest and the lowest gains are 8.2mW and 24.9mW respectively. A new technique for designing uniform multistage amplifiers (MA) for high frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. It has several advantages, such as tunability of bandwidth and decreased sensitivity of amplifier stages, to process variations. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Two six-stage amplifiers in a TSMC 0.35?m CMOS process were designed using the proposed topology. Measurements show that the gain can be varied for the first one between 16dB and 44dB within the 0.7-3.2GHz bandwidth and for the second one between 13dB and 44dB within a 1.9-3.7GHz bandwidth with less than 5.2nV/?Hz noise. Although the second amplifier has a higher gain bandwidth product, it consumes more power and occupies a wider area. A technique for capacitance multiplication is utilized to design a tunable loop filter. Current and voltage mode techniques are combined to increase the multiplication factor (M). At a high input dynamic range, M is adjustable and the capacitance multiplier performs linearly at high frequencies. Drain-source voltages of paired transistors are equalized to improve matching in the current mirrors. Measurement of a prototype loop filter IC in a 0.5?m CMOS technology shows 50?A current consumption for M=50. Where 80pF capacitance is employed, the capacitance multiplier realizes an effective capacitance varying from 1.22nF up to 8.5nF.Item Modeling, Optimization and Power Efficiency Comparison of High-speed Inter-chip Electrical and Optical Interconnect Architectures in Nanometer CMOS Technologies(2012-02-14) Palaniappan, ArunInter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, has leveraged equalization techniques to operate reliably on band-limited channels at additional power and area complexity. High-bandwidth inter-chip optical interconnect architectures have the potential to address this increasing I/O bandwidth. Considering future tera-scale systems, power dissipation of the high-speed I/O link becomes a significant concern. This work presents a design flow for the power optimization and comparison of high-speed electrical and optical links at a given data rate and channel type in 90 nm and 45 nm CMOS technologies. The electrical I/O design framework combines statistical link analysis techniques, which are used to determine the link margins at a given bit-error rate (BER), with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate and process node for three different channels. The transmitter output swing is scaled to operate the link at optimal power efficiency. Under consideration for optical links are a near-term architecture consisting of discrete vertical-cavity surface-emitting lasers (VCSEL) with p-i-n photodetectors (PD) and three long-term integrated photonic architectures that use waveguide metal-semiconductor-metal (MSM) photodetectors and either electro-absorption modulator (EAM), ring resonator modulator (RRM), or Mach-Zehnder modulator (MZM) sources. The normalized transistor parameters are applied to jointly optimize the transmitter and receiver circuitry to minimize total optical link power dissipation for a specified data rate and process technology at a given BER. Analysis results shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing, allows electrical links to achieve excellent power efficiency at high data rates. While the high-loss channel is primarily limited by severe frequency dependent losses to 12 Gb/s, the critical timing path of the first tap of the decision feedback equalizer (DFE) limits the operation of low-loss channels above 20 Gb/s. Among the optical links, the VCSEL-based link is limited by its bandwidth and maximum power levels to a data rate of 24 Gb/s whereas EAM and RRM are both attractive integrated photonic technologies capable of scaling data rates past 30 Gb/s achieving excellent power efficiency in the 45 nm node and are primarily limited by coupling and device insertion losses. While MZM offers robust operation due to its wide optical bandwidth, significant improvements in power efficiency must be achieved to become applicable for high density applications.Item The design of GaAs HEMT and HBT Bessel-type transimpedance amplifiers(Texas A&M University, 2007-04-25) Adeyemi, Oluwafemi IbukunoluwaThe need of the everyday user to transfer large amounts of data is driving the need for larger data transfer capacity. Optical communication networks can satisfy this need. To be economically viable, optical transceivers must be integrated onto chips at low cost, using relatively cheap semiconductor processes. The optical preamplifier (transimpedance amplifier) receives optical information and converts it to a useful electrical form. It must operate at high speed, contribute little distortion to the input signal, and add little electrical noise to the incoming signal. This thesis investigates the design techniques in the literature, and proposes new architectures. Two high performance preamplifiers are designed, one using GaAs HEMTs, and the other using GaAs HBTs, each with different circuit techniques. The HEMT preamplifier has a transimpedance gain of 1.4 k??????, the highest in the literature for 10 Gb/s operation, along with a low input referred noise current of about 15 pA/Hz1/2 at a bandwidth of 6.3 GHz. The HBT preamplifier also has a transimpedance gain of 1.5 k??????, with a low input referred noise current of about 7 pA/Hz1/2. Both have clear, open eye-diagrams with a 10 Gb/s bit stream input, and are suitable for integration on a chip. The HEMT preamplifier was implemented as a common-gate, common-source amplifier cascade with a darlington output driver for a 50 ?????? load. The HBT preamplifier was implemented as common-emitter darlington amplifier with shunt peaking, and a simple emitter degenerated output driver for a 50 ?????? load. Both implementations exceeded the bandwidth, transimpedance gain and noise performance typically expected of the transistor technologies used. It is shown that the transimpedance limit can be circumvented by the use of novel architectures and shunt peaking.