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Item Experimental Testing of an Electrical Submersible Pump Undergoing Abrasive Slurry Erosion(2013-04-01) Saleh, Ramy Moaness MThe Electrical Submersible Pump (ESP) manufactured by Baker Hughes, model no. WJE-1000 is designed for wells that are expected to have a high content of abrasive solids. It is a mixed flow, tandem compression type pump. Although the erosion of the pump diffuser and impeller stages are significant, the ESP study shows that the most sever failure is due to components that affect the pump?s rotor dynamics such as radial bearings and impeller seals when eroded with 100 mesh sand. Erosion of these seals will result in an internal leakage that can significantly affect stage pressure rise, efficiency, power consumption, vibration, pump life and running cost. The erosion study utilizing 100 mesh fracture sand at 0.2% concentration, with the pump operating at 3600 RPM, 40 PSI intake pressure, 1150 GPM for over 117 hours comparisons are made to the pump?s baseline performance. Measurements of the rotor bearings, impeller seals and their corresponding stators showed that the wear patterns generally increase with time and differ by location. Stage 1 bearings and seals suffered the least amount of erosion and stage 3 rotor components suffered the most erosion. The maximum change in stage 3 bearing clearances was 223% and the maximum change in stage 3 impeller seal clearances was 300%. Performance wise the total pump efficiency dropped by 6.77%, the total pressure rise dropped by 6.3%, the pump?s best efficiency point decreased by 0.78%, and the power consumption increased by 0.49%. Pump vibration patterns also changed with time and by location. The maximum shaft orbit diameter was at stage 3 and it grew 643% in diameter after 117 hours of erosion. The waterfall plots of the pump?s ramp up changed significantly with time. After 117 hours at 3600 RPM, sub-synchronous oscillations at 67% of the synchronous speed dominated the amplitude peaks showing that the rotor vibration locked with the rotor?s first natural frequency at around 2500 RPM. After 117 hours, another sub-synchronous started showing a peak at the rotor?s second natural frequency at 1500 RPM.Item Path Delay Test Through Memory Arrays(2013-07-29) Pokharel, PunjMemory arrays cannot be as easily tested as other storage elements in a chip. Most of the flip-flops (FFs) in a chip can be replaced by scan cells in scan-based design. However, the bits in memory arrays cannot be replaced by scan cells, due to the area cost and the timing-critical nature of many of the paths into and out of memories. Thus, bits in a memory array can be considered non-scan storage elements. Test methods such as memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these tests aren?t sufficient to test the paths through the memory arrays. During structural (scan) test generation, memory arrays are treated as ?black boxes? or memory arrays are bypassed to a known value. Black boxes decrease coverage loss while bypassing increases chip area and delay. Path delay test through memory arrays is proposed using pseudo functional test (PFT) with K Longest Paths Per Gate (KLPG). In this technique, any longest path that is captured into a non-scan cell (including a memory cell) is propagated to a scan cell. The propagation of the captured value from non-scan cell to scan cell occurs during low-speed clock cycles. In this work, we assume that only one extra coda cycle is sufficient to propagate the captured value to a scan cell. This is true if the output of the memory feeds combinational logic that in turn feeds scan cells. When we want to launch a transition from a memory output, different values are written into different address locations and the address is toggled between the locations. The ATPG writes the different values into the memory cells during the preamble cycles. In the case of launching a transition out of a non-scan cell, the cell must be written with an initial value during the preamble cycles, and the next value set on the non-scan cell input. Thus, it is possible to capture and launch transitions into and from memory and non-scan cells and thus test the path delay of the longest paths into and out of memory and non-scan cells.Item Test Submission(2015-02) Submitter, TestThis is a sample submission generated by Vireo to test the repository deposit features.