Browsing by Subject "Strained silicon"
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Item Developing and implementing a Raman NSOM for the characterization of semiconductor materials(2010-05) Furst-Pikus, Greyhm Matthew; Campion, Alan; Barbara, Paul; Mullins, C. B.; Stevenson, Keith J.; Vanden Bout, David A.We have designed and constructed a novel Raman near-field scanning optical microscope (NSOM) and evaluated its performance characteristics with the goal of characterizing the strain in nanoscopic silicon structures. The Raman NSOM was built around a commercial Raman microscope to which a custom built stage was added to provide precise control over the tip position above the sample (z) using shear-force microscopy feedback as well as sample scanning in the x-y plane. The motion control axes were calibrated to better than 1 nm in z and approximately 20 nm in x and y. The NSOM provides both topographical images and Raman mapping with a lateral spectral resolution of 150-300 nm. The experiments described herein were enabled by gold-coated chemically etched NSOM tips with aperture diameters ranging between 60 and 150 nm. The sensitivity of the instrument was demonstrated by the high signal-to-noise ratios observed for Raman scattering by diamond and silicon in reflection mode. Spatial resolution and spectral sensitivity were demonstrated by obtaining well-resolved tip-sample separation curves that provide an accurate estimate of tip aperture size during an experiment.Item Enhancement of integrated circuits performance : metal gate electrodes and strained silicon MOSFETs(2006-05) Thareja, Gaurav; Lee, Jack Chung-YeungEnhancement of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device performance has been achieved by work function engineering of Metal gates (controlling and lowering threshold Voltage (VTH)) and incorporating Strained Silicon as a substrate (higher mobility of the carriers). However there has not been any report on successful demonstration of low work function MOS Metal Gate Electrode and reliability of MOS Strained SOI devices. The thesis investigates a novel approach of tuning the work function of thermally stable Tantalum Nitride (TaN) metal gate using a Gadolinium buffer layer on Hafnium based high-k gate dielectrics. An NMOS compatible low work function metal gate resulting in lower VTH, has been successfully demonstrated. The thesis also explores the Bias Temperature Instability (BTI reliability) of the Strained Silicon on Insulator (S-SOI) MOSFETs for the first time. Degraded Reliability has been observed on strained devices and a plausible mechanism has been proposed.