Browsing by Subject "Receiver"
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Item Circuit techniques for programmable broadband radio receivers(2013-12) Forbes, Travis Michael, 1986-; Gharpurey, RanjitThe functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF.Item Development and testing of a miniaturized, dual-frequency, software-defined gps receiver for space applications(2011-12) Joplin, Andrew Jonathan; Lightsey, E. Glenn; Humphreys, ToddWhile dual-frequency GPS receivers have been used in space for more than two decades, the size, power, and cost of this technology is an important driver for future space missions. The growing availability of launch opportunities for very small satellites known as nanosatellites and CubeSats raises the possibility of more affordable access to space measurements if the observation quality is sufficient to support the user's needs. This thesis presents the initial development and testing of the Fast, Orbital, TEC, Observables, and Navigation (FOTON) receiver: a small, reconfigurable, dual-frequency, space-based GPS receiver. Originally developed as a science-grade software receiver for monitoring ionospheric scintillation and total electron content (TEC), this receiver was designed to provide high-quality GPS signal observations. The original receiver hardware was miniaturized and the software has been adapted for low earth orbit (LEO) operations. FOTON now fits within a 0.5U CubeSat form factor (8.3 x 9.6 x 3.8 cm), weighs 326 g, and consumes 4.5 W of instantaneous power, which can be reduced to <1 W orbit average power with on-off duty cycling. The receiver has been designed with commercial parts to keep manufacturing costs low. Significant testing of FOTON has been performed with live signals and with signals generated by a Spirent GPS signal simulator. Initial terrestrial tests demonstrate behavioral consistency with the original heritage high-performance receiver. Several LEO simulations are presented, demonstrating FOTON's single-frequency and dual-frequency-enhanced positioning down to 0.5 m and 1.5 m, respectively, which can be improved using Kalman filter based POD. FOTON's potential for GPS radio occultation observation is also demonstrated. In addition, its acquisition and reacquisition performance is presented; on average, FOTON's time to first fix is approximately 45 seconds. Finally, navigation in geostationary orbit (GEO), a challenging application for space-based GPS receivers, is demonstrated. Extensive testing demonstrates that FOTON is a robust, versatile, high-precision dual-frequency space receiver. Its low cost, size, weight, and power requirements are key enablers for future small-satellite missions.Item High performance RF and baseband building blocks for wireless receivers(Texas A&M University, 2007-09-17) Bahmani, FaramarzBecause of the unique architecture of wireless receivers, a designer must understand both the high frequency aspects as well as the low-frequency analog considerations for different building blocks of the receiver. The primary goal of this research work is to explore techniques for implementing high performance RF and baseband building blocks for wireless applications. Several novel techniques to improve the performance of analog building blocks are presented. An enhanced technique to couple two LC resonators is presented which does not degrade the loaded quality factor of the resonators which results in an increased dynamic range. A novel technique to automatically tune the quality factor of LC resonators is presented. The proposed scheme is stable and fast and allows programming both the quality factor and amplitude response of the LC filter. To keep the oscillation amplitude of LC VCOs constant and thus achieving a minimum phase noise and a reliable startup, a stable amplitude control loop is presented. The proposed scheme has been also used in a master-slave quality factor tuning of LC filters. An efficient and low-cost architecture for a 3.1GHz-10.6GHz ultra-wide band frequency synthesizer is presented. The proposed scheme is capable of generating 14A novel pseudo-differential transconductance amplifier is presented. The proposed scheme takes advantage of the second-order harmonic available at the output current of pseudo-differential structure to cancel the third-order harmonic distortion. A novel nonlinear function is proposed which inherently removes the third and the fifth order harmonics at its output signal. The proposed nonlinear block is used in a bandpass-based oscillator to generate a highly linear sinusoidal output. Finally, a linearized BiCMOS transconductance amplifier is presented. This transconductance is used to build a third-order linear phase low pass filter with a cut-off frequency of 264MHz for an ultra-wide band receiver. carrier frequencies.Item System and Circuit Design Techniques for Silicon-based Multi-band/Multi-standard Receivers(2011-08-08) El-Nozahi, Mohamed A.Today, the advances in Complementary MetalOxideSemiconductor (CMOS) technology have guided the progress in the wireless communications circuits and systems area. Various new communication standards have been developed to accommodate a variety of applications at different frequency bands, such as cellular communications at 900 and 1800 MHz, global positioning system (GPS) at 1.2 and 1.5 GHz, and Bluetooth andWiFi at 2.4 and 5.2 GHz, respectively. The modern wireless technology is now motivated by the global trend of developing multi-band/multistandard terminals for low-cost and multifunction transceivers. Exploring the unused 10-66 GHz frequency spectrum for high data rate communication is also another trend in the wireless industry. In this dissertation, the challenges and solutions for designing a multi-band/multistandard mobile device is addressed from system-level analysis to circuit implementation. A systematic system-level design methodology for block-level budgeting is proposed. The system-level design methodology focuses on minimizing the power consumption of the overall receiver. Then, a novel millimeter-wave dual-band receiver front-end architecture is developed to operate at 24 and 31 GHz. The receiver relies on a newly introduced concept of harmonic selection that helps to reduce the complexity of the dual-band receiver. Wideband circuit techniques for millimeterwave frequencies are also investigated and new bandwidth extension techniques are proposed for the dual-band 24/31 GHz receiver. These new techniques are applied for the low noise amplifier and millimeter-wave mixer resulting in the widest reported operating bandwidth in K-band, while consuming less power consumption. Additionally, various receiver building blocks, such as a low noise amplifier with reconfigurable input matching network for multi-band receivers, and a low drop-out regulator with high power supply rejection are analyzed and proposed. The low noise amplifier presents the first one with continuously reconfigurable input matching network, while achieving a noise figure comparable to the wideband techniques. The low drop-out regulator presented the first one with high power supply rejection in the mega-hertz frequency range. All the proposed building blocks and architecture in this dissertation are implemented using the existing silicon-based technologies, and resulted in several publications in IEEE Journals and Conferences.