Browsing by Subject "Quantum-dot cellular automata"
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Item Design of parallel multipliers and dividers in quantum-dot cellular automata(2011-05) Kim, Seong-Wan; Swartzlander, Earl E.; Ambler, Anthony P.; Driga, Mircea D.; Gouda, Mohamed G.; Touba, Nur A.; Schulte, Michael J.; Bickerstaff, K'Andrea C.Conventional CMOS (the current dominant technology for VLSI) implemented with ever smaller transistors is expected to encounter serious problems in the near future with the need for difficult fabrication technologies. The most important problem is heat generation. The desire for device density, power dissipation and performance improvement necessitates new technologies that will provide innovative solutions to integration and computations. Nanotechnology, especially Quantum-dot Cellular Automata (QCA) provides new possibilities for computing owing to its unique properties. Numerous nanoelectronic devices are being investigated and many experimental devices have been developed. Thus, high level circuit design is needed to keep pace with changing physical studies. The circuit design aspects of QCA have not been studied much because of its novelty. Arithmetic units, especially multipliers and dividers play an important role in the design of digital processors and application specific systems. Therefore, designs for parallel multipliers and dividers are presented using this technology. Optimal design of parallel multipliers for Quantum-Dot Cellular Automata is explored in this dissertation. As a main basic element to build multipliers, adders are implemented and compared their performances with previous adders. And two different layout schemes that single layer and multi-layer wire crossings are compared and analyzed. This dissertation proposes three kinds of multipliers. Wallace and Dadda parallel multipliers, quasi-modular multipliers, and array multipliers are designed and simulated with several different operand sizes. Also array multipliers that are well suited in QCA are constructed and formed by a regular lattice of identical functional units so that the structure is conformable to QCA technology without extra wire delay. All these designs are constructed using coplanar layouts and compared with other QCA multipliers. The delay, area and complexity are compared for several different operand sizes. This research also studies divider designs for quantum-dot cellular automata. A digit recurrence restoring binary divider is a conventional design that serves as a baseline. By using controlled full subtractor cell units, a relatively simple and efficient implementation is realized. The Goldschmidt divider using the new architecture (data tag method) to control the various elements of the divider is compared for the performance.Item Modified non-restoring division algorithm with improved delay profile(2011-05) Jun, Kihwan; Swartzlander, Earl E.; Driga, Mircea D.This thesis focuses on reducing the delay of non-restoring division. Although the digit recurrence division is lower in complexity and occupies a smaller area than division by convergence, it has a drawback: slow division speed. To mitigate this problem, two modification ideas are proposed here for the non-restoring division, the fastest division algorithm of the digit recurrence division methods. For the first proposed approach, the delay of the multiplexer for selecting the quotient digit and determining the way to calculate the partial remainder can be reduced through inverting the order of its flowchart. Second, one adder and one inverter can be removed by using a new quotient digit converter. To prove these ideas are valid, the simulation results comparing the modified non-restoring division and the standard non-restoring division are provided.