Browsing by Subject "Power amplifier"
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Item High performance pulse width modulated CMOS class D power amplifiers(2012-12) Lu, Jingxue; Gharpurey, RanjitThe objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation.Item System modeling of CMOS power amplifier employing envelope and average power tracking for efficiency enhancement(2012-08) Tintikakis, Dimitri; Gharpurey, RanjitIn the past decade, there has been great motivation to improve the efficiency of power amplifiers (PAs) in handset transmitter systems in order to address critical issues such as poor battery life and excessive heat. Currently, the focus lies on high data rate applications such as wideband code division multiple access (WCDMA) and long term evolution (LTE) standards due to the stringent efficiency and linearity requirements on the PA. This thesis describes a simulation-based study of techniques for enhancing the efficiency of a CMOS power amplifier for WCDMA and LTE applications. The primary goal is to study the concepts of envelope and average power tracking in simulation and to demonstrate the effectiveness of these supply modulation techniques on a CMOS PA design. The P1dB and IMD performance of a Class A/AB CMOS PA has been optimized to operate with high peak-to-average modulation with WCDMA and LTE signals. Behavioral models of envelope and average power tracking are implemented using proposed algorithms, and a system-level analysis is performed. Envelope tracking is seen to offer a peak PAE improvement of 15% for WCDMA, versus a fixed voltage supply, while average power tracking renders a maximum efficiency gain of 9.8%. Better than -33dBc adjacent channel leakage-power ratio (ACLR) at 5MHz offset and EVM below 4% are observed for both supply tracking techniques. For LTE, envelope and average power tracking contribute to a peak PAE enhancement of 15.3% and 7%, respectively. LTE ACLR begins failing the -30dBc specification above 22.5dBm output power during envelope tracking operation in the PA implementation described here.