Browsing by Subject "Physical design"
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Item Design of circuits for sub-threshold voltages : implementation of adders(2016-05) Giliyar Shanthir, Ankith; Swartzlander, Earl E., Jr., 1945-; Touba, Nur A.The demand and the need for low-power circuits is an ever increasing trend particularly due to the added overhead of design of efficient cooling systems or more sophisticated and expensive packaging techniques. In most new emerging applications that demand low power consumption such as biomedical implants, wearable devices, micro-sensor nodes and countless others, energy efficiency emphasis far supersedes the traditional focus on improving the speed. Such energy constrained systems can be operated at considerably reduced performance levels in order to save power and extend their battery lifetimes. Sub-Threshold design has proven useful for ultra-low power and low energy applications since the dynamic power is reduced quadratically with supply voltage; the least energy operation usually takes place in the sub-threshold region. This work provides a comprehensive analysis of the CMOS standard cell characterization in the sub-threshold region, layout, logical library extraction, optimization and top-level implementation of 2 of the parallel prefix adders of different word sizes in 45nm technology with comparison between the sub-threshold region and strong inversion regions of operation. The analysis is done on PPA: power (energy), performance and area, the common metrics for any chip design. The switching activities of the circuits were captured using dynamic gate level simulation to perform the time based peak power analysis. Static timing analysis was performed to estimate the delay of the critical path for each circuit. The analysis and results presented in this report will be helpful in choosing a specific adder configuration for an integrated circuit based on the constraints related to its application.Item Lithography aware physical design and layout optimization for manufacturability(2014-05) Gao, Jhih-Rong; Pan, David Z.As technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.