Browsing by Subject "Nanowire"
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Item Confined electron systems in Si-Ge nanowire heterostructures(2011-08) Dillen, David Carl; Tutuc, Emanuel, 1974-; Banerjee, Sanjay K.Semiconductor nanowire field-effect transistors (NWFET) have been recognized as a possible alternative to silicon-based CMOS technology as traditional scaling limits are neared. The core-shell nanowire structure, in particular, also allows for the enhancement of carrier mobility through radial band engineering. In this thesis, we have evaluated the possibility of electron confinement in strained Si-Si1-xGex core-shell nanowire heterostructures. Cylindrical strain distribution was calculated analytically for structures of various dimensions and shell compositions. The strain-induced conduction band edge shift of each region was found using k•p theory coupled with a coordinate system shift to account for strain. A positive conduction band offset of up to 200 meV was found for a Si-Si0.2Ge0.8 structure. We have also designed and characterized a modulation doping scheme for p-type, Ge-SiGe core-shell NWFETs. Finite element simulations of hole density versus radial position were done for different combinations of dopant position and concentration. Three modulation doped nanowire samples, each with a different boron doping density in the shell, were grown using a combined vapor-liquid-solid and chemical vapor deposition process. Low temperature current-voltage measurements of bottom- and top-gate samples indicate that hole mobility is limited by the proximity of charged impurities.Item Design and characterization of nanowire array as thermal interface material for electronics packaging(2009-05-15) Chiang, Juei-ChunTo allow electronic devices to operate within allowable temperatures, heat sinks and fans are employed to cool down computer chips. However, cooling performance is limited by air gaps between the computer chip and the heat sink, due to the fact that air is a poor heat conductor. To alleviate this problem, thermal interface material (TIM) is often applied between mating substrates to fill air gaps. Carbon nanotube (CNT) based TIM has been reported to have excellent thermal impedance; however, because it is non biodegradable, its potential impact on the environment is a concern. In this thesis research, two types of TIMs were designed, synthesized, and characterized. The first type, Designed TIM 1, consisted of anodic aluminum oxide (AAO) templates with nanochannels (pore size=80nm) embedded with copper nanowires by electrodeposition. This type of nanostructure was expected to have low thermal impedance because the forest-like structure of copper nanowires can bridge two mating surfaces and efficiently transport heat one dimensionally from one substrate to the other. The second type, Designed TIM 2, was fabricated by sandwiching Designed TIM 1 with commercially available thermal grease to further reduce thermal impedance. It was expected that the copper nanowire structures would secure the thermal grease in place, thus preventing grease pump-out under contact pressure, which is a common problem associated with the usage of thermal grease. The morphologies of the two designed TIMs were studied using scanning electron microscopy (SEM), and their thermal properties were determined using ASTM D5470-06, the standard method for testing thermal transmission properties of thermally conductive materials. Experiments were conducted to evaluate the proposed TIMs, as well as commercially available TIMs, under different temperature and pressure settings. Experimental results suggest that the thermal impedance of TIMs can be reduced by increasing contact pressure or reducing thickness. Designed TIM 2 yielded 0.255?-cm2/W, which is lower than thermal grease and other available TIMs at the operating temperature of 50 to 60?. Considering the application limitations and safety issues of thermal grease, phase change material, and CNT-based TIMs, our designed TIMs are safe and promising for future applications.Item Electrical and Optical Characterization of Nanoscale Materials for Electronics(2012-10-05) Chang, Chi-Yuan 1980-Due to a lack of fundamental knowledge about the role of molecular structures in molecular electronic devices, this research is focused on the development of instruments to understand the relation between device design and the electronic properties of electroactive components. The overall goal is to apply this insight to obtain a more efficient and reliable scheme and greater functional control over each component. This work developed a fabrication method for porphyrinoids on graphene-based field effect transistors (FETs), and a chemical sensing platform under an ambient environment by integrating a tip-enhanced Raman spectroscope (TERS), atomic force microscope (AFM), and electronic testing circuit. The study is divided into three aspects. The first is aimed at demonstrating fabrication processes of nanoscale FETs of graphene and porphyrinoid composites based entirely on scanning probe lithography (SPL). A nanoshaving mechanism was used to define patterns on octadecanethiol self-assembled monolayers on gold film evaporated on graphene flakes, followed by metal wet etching and/or oxygen plasma etching to develop patterns on Au films and graphene, respectively. The integrity and optoelectronic properties were examined to validate the processes. The second area of study focused on the development of the chemical sensing platform, enabling chemical changes to be monitored during charge transports under an ambient environment. The localized Raman enhancement was induced by exciting surface plasmon resonance in nanoscale silver enhancing probes made by thermal silver evaporation on sharp AFM tips. As the system was designed along an off-axis illumination/collection scheme, it was demonstrated that it was capable of observing molecular decomposition on opaque and conductive substrates induced by an electric bias. The third line of work proposed a novel TERS system and a probe preparation method. Silver nanowires mounted on AFM tips were used to locally enhance the Raman scattering. The observed Raman enhancement allows quick chemical analysis from a nanoscale region, and thus enables chemical mapping beyond the diffraction limit. Compared with other TERS geometries, the new optical design not only allows analysis on large or opaque samples, but also simplifies the design of the optical components and the alignment processes of the setup.Item Epitaxial germanium via Ge:C and its use in non-classical semiconductor devices(2015-12) Mantey, Jason Christopher; Banerjee, Sanjay; Lee, Jack C; Register, Leonard F; Akinwande, Deji; Ferreira, Paulo JThe microelectronics industry has been using Silicon (Si) as the primary material for complementary metal-oxide-semiconductor (CMOS) chip fabrication for more than six decades. Throughout this time, these CMOS devices have gotten exponentially smaller, faster, and cheaper. While new materials and fabrication processes have been slowly added over the years, the CMOS device of today is largely the same as it was decades ago. However, field-effect transistors (FETs) have now scaled so far that Si is approaching physical limits. Thus, new channel materials and new fundamental device structures are being investigated to replace traditional CMOS. Germanium is one of the prime candidates to replace Si in the FET channel, with its increased electron and hole mobilities compared to Si. Perhaps more importantly, it is compatible with the existing Si manufacturing techniques by epitaxially growing thin layers of Ge crystal on the starting Si wafer. Because these two crystals do not share a lattice constant, there will inevitably be crystal defects in the thin Ge layer that can be catastrophic for device functionality. Several approaches have been introduced to reduce defects, but most of them are wastefully thick (>1 um) or require complex manufacturing methods. In this work, we utilize an extremely thin (~10 nm) buffer layer of carbon-doped Ge (Ge:C) to grow Ge and SiGe layers for FET and virtual substrate applications with improved crystalline quality and reduced surface roughnesses. These thin Ge layers not only offer new pathways for MOSFETs, but can also be used in non-classical structures. Semiconductor nanowires (NWs) and tunnel-FETs (TFETs) are two of the most promising device architectures, and both can be used with Ge. This dissertation presents a simulated Si/Ge heterostructure interface TFET that can be fabricated on a virtual substrate made with the Ge:C buffer layer. Detailed analysis on device operation is given. Also in this work is the fabrication process for individually addressable Ge NW-FETs. The NWs offer excellent electrostatic gate control through reduced dimensions and offer another potential pathway for Ge in a post-CMOS world.Item Novel 3-D IC technology(2014-05) Zhai, Yujia; Banerjee, Sanjay; Willson, C. G. (C. Grant), 1939-For many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).Item Silicon nanowires : synthesis and use as lithium-ion battery anodes(2014-12) Bogart, Timothy Daniel; Korgel, Brian Allan, 1969-; Mullins, C. Buddie; Ekerdt, John G.; Chelikowsky, James R.; Manthiram, ArumugamAs the power demands of mobile technologies continue to increase, lithium-ion batteries are needed with greater power and energy density. Silicon anodes offer an alternative to commercial graphite with much greater gravimetric and volumetric Li storage. Si nanowires are particularly compelling anode materials because they provide short Li diffusion paths due to their narrow diameter combined with long continuous paths for electron transport down their length. To achieve reasonable battery performance in Si nanowire anodes, conductive carbon particles must be added to provide sufficient electrical conductivity through the anode layer. This lowers the capacity of the anode, but more importantly the carbon particles can segregate in the electrode layer during processing or as a result of mechanical stresses during cycling, leading to unreliable performance. Better performance can be achieved by altering the structure of the Si nanowire to improve electrical conductivity. Si nanowires with a conductive carbon coating were synthesized in a supercritical organic solvent using an organometallic tin precursor to seed growth. The coating eliminated the need for additional conductive additives and improved Si nanowire anode performance. In situ TEM experiments showed that the coated nanowires exhibit higher lithiation rates than bare Si nanowires, but the coating restricts volume expansion limiting the amount of Li storage. Nanowires with a crystalline Si core and amorphous Si shell were also synthesized. The thickness of the core and shell were controlled by altering the Si:Sn precursor ratio. Sn was found to incorporate strongly within the crystalline core, but not at all in the amorphous shell, creating nanowires with varying conductivity. The addition of tin improved Si nanowire performance in Li-ion batteries, eliminating the need for conductive additives. Lastly, the low-temperature limit on the solution synthesis of Si nanowires via in situ seeding was explored using tin, gallium, and indium seeds.Item Simulation of a plasmonic nanowire waveguide(2009-05) Malcolm, Nathan Patrick; Howell, John R.; Shi, LiIn this work a Finite Difference Time Domain (FDTD) simulation is employed to explore local field enhancement, plasmonic coupling, and charge distribution patterns. This 3D simulation calculates the magnetic and electric field components in a large matrix of Yee cells using Maxwell’s equations. An absorbing boundary condition is included to eliminate reflection back into the simulation chamber, and a sample system of cells is checked for convergence. In the specific simulations considered here, a laser pulse of single wavelength is incident on a silicon substrate, travels through an embedded ZnO nanowire (NW) waveguide only (due to an Ag filter), then incites plasmonic coupling at the gap between an Au nanoparticle tip and an Au substrate, an Au nanoparticle (NP), or a trio of Au nanoparticles incident on an angled Si substrate. The angle between the axis of the NW and the normal of the substrate is varied from 0-60°. The NP perpendicular deflection with respect to the NW axis is also varied from -115 - 75 nm. The enhancement patterns reveal superior signal to noise ratio compared to Near Field Scanning Optical Microscopy (NSOM), three times smaller than the NP diameter 100 nm, as well as resolution and spot size of less than 50 nm. This method of Apertureless NSOM (ANSOM) using a NW waveguide grown on a transparent microcantilever therefore shows promise for imaging of single molecules incident on a substrate and NP-labeled cell membrane.Item Strain and modulation doping in epitaxial Si/Ge core-shell nanowire heterostructures(2015-12) Dillen, David Carl; Tutuc, Emanuel, 1974-; Banerjee, Sanjay K; Dodabalapur, Ananth; Yu, Edward T; Korgel, Brian AFor over five decades, silicon based electronics relied on scaling of individual field-effect transistors (FETs) for improvements in integrated circuit performance. Recently, however, further enhancement of packing density and switching speed was limited by the increase in power consumption of short channel devices. New materials and device geometries were introduced to help expand CPU performance while also decreasing power dissipation. Semiconducting nanowires have also been recognized for potential applications as channel material in highly scaled FETs. These structures present opportunities for strain and energy band engineering through the use of radial, or core-shell, heterostructures. To fully exploit the benefits of radial heterostructures, however, requires knowledge of elastic strain distributions and energy band alignments, necessitating the development of new characterization methods. This is especially true in Si/Ge material systems, where a large lattice mismatch over 4% is possible. In this thesis, we grow Si/Ge core-shell nanowires and demonstrate multiple techniques to characterize the nanoscale heterostructure, including strain measurements and extraction of valence band offsets. We grow Ge-SixGe1-x core-shell nanowires and measure the elastic strain using Raman spectroscopy. The Ge core’s Raman spectrum is consistent with a compressive strain in this region due to lattice mismatch with the SixGe1-x shell. The strain distribution and expected Raman peak positions are calculated using continuum elasticity models and lattice dynamic theory, finding excellent agreement to experimental data. We also demonstrate radial modulation doping in Ge-SixGe1-x core-shell nanowire heterostructures by doping a portion of the SixGe1-x shell with boron during growth. The modulation doped nanowire FETs show an enhanced low temperature hole mobility and also a decoupling of transport between core and shell. Through comparison to finite-element calculations, we extract the valence band offset at the core-shell interface. Lastly, we grow coherently strained Si-SixGe1-x core-shell nanowires and characterize the structure using Raman spectroscopy. We first optimize the Si nanowire growth process to favor the diamond crystal structure and to minimize sidewall coverage by Au catalyst, followed by epitaxial growth of the SixGe1-x shell using the Si nanowire as substrate. Raman measurements on core-shell samples indicate a tensile strain in the Si core and a compressive strain in the SixGe1-x shell, both consistent with calculations of the strain and the strain-induced shift of the Raman peaks in this structure.Item Superconducting Proximity Effect in Single-Crystal Nanowires(2010-07-14) Liu, HaidongThis dissertation describes experimental studies of the superconducting proximity effect in single-crystal Pb, Sn, and Zn nanowires of lengths up to 60 um, with both ends of the nanowires in contact with macroscopic electrodes that are either superconducting (Sn or Pb) or non-superconducting (Au). The Pb, Sn, and Zn nanowires are fabricated using a template-based electrochemical deposition method. Electric contacts to the nanowires are formed in situ during electrochemical growth. This method produces high transparency contacts between a pair of macroscopic electrodes and a single nanowire, circumventing the formation of oxide or other poorly conducting interface layers. Extensive analyses of the structure and the composition of the nanowire samples are presented to demonstrate that (1) the nanowires are single crystalline and (2) the nanowires are clean without any observable mixing of the materials from the electrodes. The nanowires being investigated are significantly longer than the nanowires with which electrode-induced superconductivity was previously investigated by other groups. We have observed that in relatively short (~6 um) Sn and Zn nanowires, robust superconductivity is induced at the superconducting transition temperatures of the electrodes. When Sn and Pb nanowires are in contact with a pair of Au electrodes, superconductivity is suppressed completely. For nanowires of 60 um in length, although the suppression of superconductivity by Au electrodes is only partial, the induced superconductivity at the higher transition temperatures of the electrodes remains full and robust. Therefore, an anomalous superconducting proximity effect has been observed on a length scale which far exceeds the expected length based on the existing theories of the proximity effect. The measured current-voltage characteristic of the nanowires reveals more details such as hysteresis, multiple Andreev reflection, and phase-slip centers. An interesting relation between the proximity effect and the residual-resistance-ratio of the nanowires has also been observed. Possible mechanisms for this proximity effect are discussed based on these experimental observations.Item Thermal and thermoelectric transport in organic and inorganic nanostructures(2012-08) Weathers, Annie C.; Shi, Li, Ph. D.; Tutuc, EmanuelThermal transport in nanowires and nanotubes has attached much attention due to their use in various functional devices and their use as a model system for low dimensional transport phenomena. The precise control of the crystal structure, defects, characteristic size, and electronic properties of nanowires has allowed for fundamental studies of phonon and electron transport in a variety of nanoscale systems. The thermal conductivity in nanostructured materials can vary greatly compared to bulk values owing to classical and quantum size effects. In this work, two model systems for investigating fundamental phonon transport were investigated for potential use in thermoelectric and thermal management applications. The thermoelectric properties of twin defect indium arsenide nanowires and the thermal conductivity of polythiophene nanofibers with improved polymer chain crystallinity were measured with a microfabricated measurement device. The effects of twin planes on reducing the mean free path of phonons in indium arsenide and the effects of improved chain alignment in increasing the thermal conductivity in polymer fibers is discussed.