Browsing by Subject "Motherboards (Microcomputers)"
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Item Centralized optical backplane bus using holographic optical elements for high performance computing(2007) Bi, Hai, 1975-; Chen, Ray T.Optical communication is distinguished for its enormous interconnect capacity over long distance. As the cost of optical components drops, high bandwidth optical systems were successfully employed into local area network and computer racks because electrical counterparts are not able to deal with the data rate demands for these applications. With the popularity of multi-core CPU in High Performance Computers, the board-to-board interconnects exclusive based on electrical technology in backplane applications become insufficient because of not only bandwidth crises, but also wiring congestions. Many researches have projected that the progress of optical technology will further push down the boundary demarcating electrical and optical domains in the interconnect hierarchy. Accordingly, backplane or even board-to-board level interconnects will benefit from the complement of optical interconnect. From architecture point of view, an optical bus implementation of the optical interconnect has the potential advantage of both huge bandwidth and elimination of wiring congestion. In contrast, optical waveguide and free-space interconnects although provide high bandwidth capacity, are essentially point-to-point technology which requires routing to a central switch on the backplane. The centralized approach that was based on substrate guided optical interconnects is the only way known that fulfills a uniform fan-out for different nodes in a bus architecture, which allows medium sharing among nodes. In this dissertation, innovative bit-interleaved optical backplane bus architecture is created based on centralized substrate-guide optical interconnect, which allows the tremendous bandwidth capacity to be shared by retaining the share bus architecture. Therefore, a secure and reliable high speed transmission channel could be established by distributing copies of confidential information separately. The feature provided by this innovative design cannot be fulfilled using electrical interconnects or other optical point-to-point technology without causing wiring congestions. In this dissertation, the optical characteristics of the centralized optical bus such as bandwidth and alignment tolerance are analyzed so that multi-channel implementation are successful on the fabricated optical interconnect layer. A 3-board-16-channel computer server using optical backplane board demonstrator using centralized optical bus was built upon the simulation, design and packaging work.Item A fractional N frequency synthesizer for an adaptive network backplane serial communication system(2005) Rangan, Giri N. K.; Swartzlander, Earl E.An architecture and design of a Phase Locked Loop based frequency synthesizer is developed in this dissertation. Using multiple phases generated by a ring oscillator, this synthesizer is able to generate non-integer multiples of the incoming, high quality clock signal. The design is done for a nominal target frequency of 3.125 GHz for application in a serial communication system such as a network backplane. Using a fully differential design, the architecture is able to achieve the stringent timing jitter requirements of a network backplane system. Advancements in the content and the coverage of the Internet have tremendously increased the need for high speed data transport over very long and very short distances. The long distance bandwidth and speed requirements have been addressed by the use of optical links. The shorter distances, such as serial communications in a network backplane are still in the realm of copper lines drawn on printed circuit boards. Thus the medium of communication places design constraints on the electronic devices operating on either side of the medium. As symbol frequencies approach 3.125 GHz and beyond, architectural modifications must be made to alleviate the channel effects. This dissertation presents a phase locked loop for a network backplane system application where the two transceivers can communicate with each other to determine a particular line code that they will use for the most optimal communication between them. The selection of the line code determines the symbol rate and in turn the transmit clock frequency. A particular line code may be chosen such that a non-integer multiple of a low frequency input clock is required. The incoming clock is usually fixed at standard frequencies like 312.5 or 625 MHz to operate the parallel data path. It would then be beneficial to have a fractional-N frequency synthesizer which can generate the necessary fractional frequency multiples. The synthesizer presented in this research work is designed in a standard 0.13 µm CMOS technology with a 1.5 V power supply. It dissipates 112 mW of power and occupies an estimated silicon area of 0.2 sq. mm. The nominal peak to peak jitter of this design is approximately 43.7 ps and the maximum peak to peak jitter is 48 ps.Item Management of complex applications in a grid computing environment(Texas Tech University, 2004-12) Jiang, ChangsuNot available