Browsing by Subject "Metal oxide semiconductors, Complementary--Design and construction"
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Item Design trade-off of low power continuous-time [Sigma Delta] modulators for A/D conversions(2007-12) Song, Tongyu; Yan, ShouliThe research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.Item Dynamic CMOS circuit power dissipation methodology in low power high bandwidth chip design(2004-05) Jeong, Taikyeong, 1969-; Ambler, TonyIn a Power Efficiency System (PES), Energy Aware Computing (EAC) is a qualitative system attribute that is quantified through specific measures at the same time. In this dissertation, a low power dynamic CMOS circuit for a power dissipation methodology will be considered as a high bandwidth communication chip design. Dynamic CMOS high performance chips and system design in Hierarchical Power Efficiency System (HPES) will be considered for high bandwidth communications while low power consumption and high speed are major design goals in the VLSI design area. In order to improve the power vs. bandwidth tradeoff, it is necessary to consider digital power dissipation methodologies and power reduction techniques. Based on experiments, we are maximizing the performance of a chip taking into account delay and power. This dissertation describes the behavior of the power dissipation tradeoff between performance and energy with dynamic and static power consumption in low power high bandwidth CMOS circuits. It also discusses a novel approach of Dynamic Multi-Threshold (DMT) logic in static power consumption. The results of computer simulations of these circuits are compared and possible improvements and applications are discussed.Item New platforms for electronic devices: n-channel organic field-effect transistors, complementary circuits, and nanowire transistors(2007-05) Yoo, Byungwook, 1975-; Dodabalapur, Ananth, 1963-This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized [alpha],[omega]-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N' --bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric/electrode surface treatment on the response of bottom-contact devices was also examined to maximize the device performance. Some of innovative techniques that employ the conducting polymer, poly(3,4-ethylenedioxythiophene) / poly(styrene sulfonate) (PEDOT/PSS) for the fabrication of OFETs, were compared and investigated. The device performance and the fabrication yield were also considered. Organic complementary ring oscillators and D flip-flops were demonstrated with PDI-8CN2 and pentacene as the n-type and ptype material, respectively. Both circuits recorded the highest speed that any organic transistor-based complementary circuit has achieved to date. The speed of these complementary circuits will be enhanced by increasing the mobility of n-channel further as well as reducing channel lengths and overlap capacitances between the source/drain electrodes and the gate. The semiconductors should be solution processible to be compatible with the inexpensive fabrication techniques envisioned for printed electronic circuits. PDI-8CN2 was used for solution-processed n-channel OFETs and the various parameters are compared for the optimization of devices. Utilizing optimized process parameters and surface treatments for solution-deposited PDI-8CN2 OFETs, we have successfully shown the first fabrication of complementary organic ring oscillators and Dflip flops by the micro-injection of the solution of both p-type and n-type materials in air. One of the potential platforms for low cost fabrication on flexible substrates is the use of inorganic semiconductor nanowires. Accordingly, the germanium nanowire FETs were fabricated and characterized. Conductivity enhanced PEDOT/PSS was employed as the electrode material for nanowire transistors to improve the electrical contacts to the source and drain.Item Novel channel materials for Si based MOS devices : Ge, strained Si and hybrid crystal orientations(2007-05) Joshi, Sachin Vineet, 1981-; Banerjee, SanjayIntegration of novel materials onto silicon substrates within a conventional CMOS framework is one of the most challenging problems facing the semiconductor industry. The evaluation of various novel channel materials such as Ge, strained Si and their alternative crystal orientations for high performance MOS devices is discussed. Techniques including the use of ultra-thin dislocation blocking layers for the epitaxial growth of Ge and strained Si, direct silicon bonding (DSB) for hybrid orientation technology (HOT) and surface passivation methods for Ge channel devices were explored in an effort to improve device performance while adhering to a CMOS-like processing scheme. Devices fabricated using low thermal budget processes with deposited high-k gate insulators and metal gate electrodes yielded significant mobility enhancements for strained Si NMOSFETs, hybrid crystal orientation devices, bulk Ge PMOSFETs as well as for PMOS devices fabricated on epi Ge layers grown on (110) Si substrates. Various tradeoffs were optimized to engineer the channel region as well as source drain junctions for long channel MOSFETs. For the dislocation blocking layer technique, deep source drain implants to minimize junction leakage and an optimized strained Si layer resulted in 50% performance enhancement. In the case of DSB-HOT devices, optimized junction passivation utilized to reduce reverse diode leakage by an order of magnitude. This reduction, coupled with DSB layer thickness optimization, may enable the implementation of this technology at the 45 nm node and beyond. The electrical quality of the bond interface for DSB wafers was also evaluated. An asymmetry in the forward and reverse current voltage characteristics was observed in spite of an oxide free bond interface. This asymmetry was attributed to a new type of junction formed at the (110) / (100) Si bond interface due to a valence band offset between the two different Si surfaces. Consistent with the experimental observation, density functional theory simulations also predict the existence of such a band offset. For bulk Ge devices, a thin SiOX interfacial layer was utilized to passivate the Ge / high-k interface and demonstrate a 2X enhancement over universal Si / SiO2 hole mobility.Item A study on electrical and material characteristics of hafnium oxide with silicon interface passivation on III-V substrate for future scaled CMOS technology(2008-05) Ok, Injo, 1974-; Lee, Jack Chung-YeungThe continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO₂ gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO₂ (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x10¹⁰ eV⁻¹cm⁻²), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO₂ film. HfO₂ based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility.