Browsing by Subject "Metal oxide semiconductor field-effect transistors--Design and construction"
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Item Fabrication modeling and reliability of novel architecture and novel materials based MOSFET devices(2006) Dey, Sagnik; Banerjee, SanjayItem Metal-oxide-semiconductor devices based on epitaxial germanium-carbon layers grown directly on silicon substrates by ultra-high-vacuum chemical vapor deposition(2006) Kelly, David Quest; Banerjee, SanjayItem Silicon-based vertical MOSFETs(2004) Jayanarayanan, Sankaran; Banerjee, SanjayFor over three decades, the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has successfully undergone scaling to improve performance, and is presently at the sub-100 nm technology node. This has been possible due to several advances in the field, such as the introduction of copper interconnects, low-K dielectrics, silicided contacts, source-drain extensions, etc. Future scaling will require new materials such as strained silicon or silicon-germanium for channel mobility and drive current enhancement, high-K gate dielectrics to reduce the gate leakage current, and novel devices such as vertical MOSFETs or Fin-FETs to suppress short-channel effects. In this work, we have fabricated sub-100 nm silicon-based vertical MOSFETs, such as 70 nm strained and unstrained silicon-germanium vertical MOSFETs, 90 nm vertical MOSFETs with hafnium-oxide gate dielectric deposited by chemical vapor deposition (CVD), and a novel 50 nm Dielectric Pocket Vertical MOSFET (DPV- MOSFET) that shows excellent suppression of short channel effects. All samples were grown with the help of Ultra-high Vacuum Chemical Vapor Deposition (UHVCVD). We have demonstrated improved hole mobility and drive current in the SiGe PMOSFETs with a uniform Ge profile. However, the SiGe devices also had a higher leakage current and lower breakdown voltage due to the smaller bandgap of SiGe as compared to Si. The unstrained SiGe vertical MOSFETs were grown on a relaxed SiGe virtual substrate, and did not show a mobility enhancement, indicating that the improvement in mobility in strained SiGe is due to strain in the crystal lattice and not just Ge content. We observed conformal dielectric deposition and reduced gate leakage currents in the vertical MOSFETs with hafnium-oxide deposited by Rapid Thermal Chemical Vapor Deposition. The SiGe devices with CVD-HfO2 gate dielectric showed improved drive currents. We also fabricated a novel device called the DPV-MOSFET. Introduction of a dielectric pocket at the source-channel junction results in a device with a shallower equivalent source junction depth and hence reduced short-channel effects such as VTrolloff and drain induced barrier lowering (DIBL). Simulation results indicate that the device also a higher ION/IOFF ratio.Item A study of HfO₂-based MOSCAPs and MOSFETs on III-V substrates with a thin germanium interfacial passivation layer(2008-08) Kim, Hyoung-sub, 1966-; Lee, Jack Chung-YeungSince metal-oxide-semiconductor (MOS) devices have been adopted into integrated circuits, the endless demands for higher performance and lower power consumption have been a primary challenge and a technology-driver in the semiconductor electronics. The invention of complementary MOS (CMOS) technology in the 1980s, and the introduction of voltage and physical dimension scaling in the 1990s would be good examples to keep up with the everlasting demands. In the 2000s, technology continuously evolves and seeks for more power efficiency ways such as high-k dielectrics, metal gate electrodes, strained substrates, and high mobility channel materials. As a gate dielectric, silicon dioxide (SiO₂), most widely used in CMOS integrated circuits, has many prominent advantages, including a high quality interface (e.g. Dit ~ low 1010 cm-2eV-1), a good thermal stability in contact with silicon (Si), a large energy bandgap and the large energy band offsets in reference to Si, and a high quality dielectric itself. As the thickness of SiO₂ keeps shrinking, however, SiO₂ is facing its physical limitations from the viewpoint of gate dielectric leakage currents and reliability requirements. High-k dielectric materials have attracted extensive attention in the last decade due to their great potential for maintaining further down-scaling in equivalent oxide thickness (EOT) and a low dielectric leakage current. HfO₂ has been considered as one of the most promising candidates because of a high dielectric constant (k ~ 20-25), a large energy band gap (~ 6 eV) and the large band offsets (> 1.5 eV), and a good thermal stability. To enhance carrier mobility, strained substrates and high mobility channel materials have attracted a great deal of attention, thus III-V compound semiconductor substrates have emerged as one of possible candidates, in spite of several technical barriers, being believed as barriers so far. The absence of high quality and thermodynamically stable native oxide, like SiO₂ on Si, has been one such hurdle to implement MOS systems on III-V substrates. However, recently, there have been a number of remarkable improvements on MOS applications on them, inspiring more vigorous research activities. In this research, HfO2-based MOS capacitors and metal-oxidesemiconductor field effect transistors (MOSFETs) with a thin germanium (Ge) interfacial passivation layer (IPL) on III-V compound substrates were investigated. It was found that a thin Ge IPL could effectively passivate the surface of III-V substrate, consequently providing a high quality interface and an excellent gate oxide scalability. N-channel MOSFETs on GaAs, InGaAs, and InP substrates were successfully demonstrated and a minimum EOT of ~ 9 Å from MOS capacitors was achieved. This research has begun with GaAs substrate, and then expanded to InGaAs, InP, InAs, and InSb substrates, which eventually helped to understand the role of a Ge IPL and to guide future research direction. Overall, MOS devices on III-V substrates with an HfO₂ gate dielectric and a Ge IPL have demonstrated feasibility and potential for further investigations.