Browsing by Subject "Metal oxide semiconductor field-effect transistors--Computer simulation"
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Item Quantum corrected full-band semiclassical Monte Carlo simulation research of charge transport in Si, stressed-Si, and SiGe MOSFETs(2006) Fan, Xiaofeng, 1978-; Banerjee, Sanjay; Register, Leonard F.This Ph.D. research is centered around a full-band Monte Carlo device simulator (“Monte Carlo at the University of Texas”, MCUT) with quantum corrections (based on one-dimensional Schrödinger equation solver). The code itself was based on a solid infrastructure of a Monte Carlo simulator, “MoCa” from the University of Illinois at Urbana-Champaign. To that there were added new methods and features during my Ph.D. program, including strained band structures, alternative (to conventional 100 ) surface orientations, full-band scattering mechanisms, and valley-dependent quantum correction. These features enable “MCUT” to be used to model various strained and/or alloyed silicon MOSFETs, as well as the MOSFETs composed of alternative materials such as Ge, in sub-100 nm regime. Monte Carlo simulation, itself, handles short channel effects and hot carriers in ultra small device well; full-band structure replaces the inaccurate and unknown (for new/strained materials) analytical formulae; and the quantum corrections approximate quantum-confinement effects on device performance. The goal is to understand and predict the device behavior of the so called “non-classical” CMOS ― beyond bulk Si based CMOS ― in the sub-100 nm regime.Item Schrödinger equation Monte Carlo-3D for simulation of nanoscale MOSFETs(2008-08) Liu, Keng-ming; Register, Leonard F.A new quantum transport simulator -- Schrödinger Equation Monte Carlo in Three Dimensions (SEMC-3D) -- has been developed for simulating the carrier transport in nanoscale 3D MOSFET geometries. SEMC-3D self-consistently solves: (1) the 1D quantum transport equations derived from the SEMC method with open boundary conditions and rigorous treatment of various scattering processes including phonon and surface roughness scattering, (2) the 2D Schrödinger equations of the device cross sections with close boundary conditions to obtain the spatially varying subband structure along the conduction channel, and (3) the 3D Poisson equation of the whole device. Therefore, SEMC-3D can provide a physically accurate and electrostatically selfconsistent approach to the quantum transport in the subbands of 3D nanoscale MOSFETs. SEMC-3D has been used to simulate Si nanowire (NW) nMOSFETs to both demonstrate the capabilities of SEMC-3D, itself, and to provide new insight into transport phenomena in nanoscale MOSFETs, particularly with regards to interplay among scattering, quantum confinement and transport, and strain.Item SiGe, SiGeC, and SiC MOSFET simulation, optimization, and fabrication(2002-12) Shi, Zhonghai; Banerjee, SanjayFor more than 30 years, MOSFET device technology has been improving at a drastic rate mainly due to successful device scaling, and the resulting increasingly smaller device dimensions and higher device performance in terms of higher packing density, higher device speed, etc. However, challenges in scaling of CMOS technology into the nanometer regime are approaching physical limits, which are very difficult to overcome, if not impossible. Since MOSFET drive current depends on carrier mobility, one way to address the challenges of improving MOS transistor performance is to enhance carrier mobility in the MOSFET channel. Compressively-strained Si1-xGex alloys are very promising in terms of increasing hole mobility. In this work, sub-micron gate length buried Si1-xGex channel PMOSFET modeling, simulation, and optimization were studied using the MEDICI simulator, and an optimized device structure is obtained. 100 nm gate length Si1- xGex channel PMOSFETs have been simulated, and optimized by the combination of process simulation (TSUPREM4) and device simulation (MEDICI). The simulation results show that the benefits of high hole mobility in a Si1-xGex channel still hold below 100nm channel length. A 100nm channel length Si1-xGex, Si1-x-yGexCy and Si1-yCy PMOSFET process was established. Not only is device performance enhancement observed but also a desirable threshold voltage (VT) and small short channel effects (SCE) are achieved by device and process optimization. Drive current enhancements are demonstrated for 100nm channel length Si1-x-yGexCy and Si1-yCy PMOSFETs compared to Si control PMOSFETs, and C provides high temperature strain-stabilization for strained Si1-xGex channels. Device performance enhancement and ease of integration can be achieved simultaneously by using a smaller Ge mole fraction and Si cap layer optimization. It is also demonstrated that surface channel operation in the Si1-xGex PMOSFET with deposited HfO2 gate dielectrics can be used to recover mobility degradation due to the use of HfO2, and device performance enhancement and leakage current reduction is achievable with this concept. In order to fully exploit the high mobility benefits of Si1-xGex, Si1-x-yGexCy, or Si1-yCy alloys, a Ni silicide technique with low resistivity for these alloys has been developed for device applications.Item Simulation study of deep sub-micron and nanoscale semiconductor transistors(2005) Xia, Tongsheng; Banerjee, Sanjay; Register, Leonard F.