Browsing by Subject "Memristor"
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Item Dynamic Modeling and Analysis for Design of Memristive and Static Random Access Memories(2014-08-27) Ho, YenpoNowadays, the trend of modern memory technology is going towards the following directions: (1) look for new nonvolatile devices; (2) keep scaling down the existing volatile devices. Although nonvolatile devices enable to switch off its power supply to further suppress standby power, the down sides are the low switching speed and the complicated dynamic cell characteristics. On the other hand, researchers are looking to scale down SRAM since it is the most reliable and fast. However, the SRAM suffers read and write failure due to lack of good stability optimizing metric. To tackle the above mentioned problems, this work first introduces a promising nonvolatile device called Memristor, which is said to be possible to replace our memory devices now. By starting from basic memristor device equations, this work aims to develop a comprehensive set of properties and design equations for memristor based memory. The introduced schemes are specifically targeting key device properties relevant to memory operations. Using the discovered properties, a simple design of read/write circuits is investigated. In the second part of this work, SRAM stability analysis is focused. SRAM verification and stability analysis has become an essential task to investigate soft-errors. This work aims to extend the SNM to a new era. Based on the introduced Region-Analysis in this work, SRAM stability can be explained using bifurcation theory, and closed form expression can be derived. The derived expression provides physical characterization of SRAM noise tolerance property; thus has potential to provide needed design insights. Overall, dynamics of memristor and SRAM are strongly emphasized. The derived memristor properties reveals that the memristor state change requires some time; it indicates that the memristor-based memory needs some ?critical time? to flip the logic. Similarly to the SRAM, the SRAM write operation not only needs the injected current over a ?critical current? but also need to maintain for some ?critical time?. In short, both memristor-based memory and SRAM show the timely manner for read/write operation. Furthermore, the developed analytical formulae are able to reveal the dynamic aspect on memory read/write operations which address the key concern for modern memory technology.Item Memristor based arithmetic circuit design(2016-12) Revanna, Nagaraja; Swartzlander, Earl E., Jr., 1945-; Valvano, Jonathan; Akinwande, Deji; Gerstlauer, Andreas; Schulte, MichaelThe revolution in electronics enabled by Moore’s Law has been driven historically by the ability to fabricate ever smaller features lithographically on planar semiconductor platforms. In recent years, this has been slowing down due to the myriad of problems in short channel CMOS technologies. Research is now focusing on realizing Moore’s law by architectural innovation, involving novel circuits and computation paradigms. There has been intense interest and activity directed towards designing logic circuits with memory elements. This is mainly driven by ideas like in-memory compute where logic operations are performed at the memory location in order to overcome the memory-wall bottleneck. Resistive-switching random-access memory (RRAM)/ memristors has a great potential to be the future of non-volatile memory owing to its CMOS compatibility, read-write endurance, power and speed. We describe novel high speed logic circuits for adders and multipliers built with RRAM to support the concept of logic-in-memory. These circuits have significant speed/area/power improvements over the existing designs. The complexity involved in computation in terms of controlling the basic gates, sequence of operations etc. has been significantly reduced. RRAM properties are exploited with the help of a well-known analog element called current mirror. Previously known logic-implication technique to realize digital gates comes with a serious limitation of limited fan-out. By using current mirrors, this limitation can be overcome, enabling more logic operations to run in parallel. Results show that the delay for even an XOR operation can be reduced to 1 cycle, compared to the 5 cycles taken by logic implication. Spice simulations are done with known RRAM models. Simulation results show significant improvement in power consumed over the existing designs. The design of different adders and multipliers are also described. Metrics like area, power and latency are compared, and it shows significant improvement over the state-of-the-art.