Browsing by Subject "MOSFET"
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Item Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices(2012-07-16) Bekal, PrasannaIn order to correctly perform circuit simulation, it is crucial that parasitic capacitances near devices are accurately extracted and are consistent with the SPICE models. Although 3D device simulation can be used to extract such parasitics, it is expensive and does not consider the effects of nearby interconnect and devices in a layout. Conventional rule-based layout parasitic extraction (LPE) tools which are used for interconnect extraction are inaccurate in modeling 3D effects near devices. In this thesis, we propose a methodology which combines 3D field solver based extraction with the ability to exclude specific parasitics from among the parameters in the SPICE model. We use this methodology to extract parasitics due to fringing fields and sidewall capacitances in MOSFETs, bipolar transistors and FinFETs in advanced process nodes. We analyze the importance of considering layout and process variables in device extraction by comparing with standard SPICE models. The results are validated by circuit simulation using predictive technology models and test chips. We also demonstrate the versatility of this flow by modeling the capacitance contributions of the raised gate profile in nanoscale FinFETs.Item III-V MOSFETs from planar to 3D(2013-08) Xue, Fei, active 2013; Lee, Jack Chung-YeungSi complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuously scaling of its feature size. As scaling is approaching its physical limitations, new materials and device structures are expected. High electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k/metal metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability. A comprehensive study on III-V MOSFETs has been presented here focusing on three areas: 1) III-V/high-k/metal gate stack: material and electrical properties of various high-k dielectrics on III-V substrates have been systematically examined; 2) device architecture: device structures from planar surface channel MOSFETs and buried channel quantum well FETs (QWFETs) to 3D gate-wrapped-around FETs (GWAFETs) and tunneling FETs (TFETs) have been designed and analyzed; 3) fabrication process: process flow has been set up and optimized to build scaled planar and 3D devices with feature size down to 40nm. Potential of high performances have been demonstrated using novel III-V/high-k devices. Effective channel mobility was significantly improved by applying buried channel QWFET structure. Short channel effect control for sub-100nm devices was enhanced by shrinking gate dielectrics, reducing channel thickness and moving from 2D planar to 3D GWAFET structure. InGaAs TFETs have also been developed for ultra-low power application. This research work demonstrates that III-V/high-k/metal MOSFETs with superior device performances are promising candidates for future ultimately scaled logic devices.Item Nanocrystals Embedded Zirconium-doped Hafnium Oxide High-k Gate Dielectric Films(2012-10-19) Lin, Chen-HanNanocrystals embedded zirconium-doped hafnium oxide (ZrHfO) high-k gate dielectric films have been studied for the applications of the future metal oxide semiconductor field effect transistor (MOSFET) and nonvolatile memory. ZrHfO has excellent gate dielectric properties and can be prepared into MOS structure with a low equivalent oxide thickness (EOT). Ruthenium (Ru) modification effects on the ZrHfO high-k MOS capacitor have been investigated. The bulk and interfacial properties changed with the inclusion of Ru nanoparticles. The permittivity of the ZrHfO film was increased while the energy depth of traps involved in the current transport was lowered. However, the barrier height of titanium nitride (TiN)/ZrHfO was not affected by the Ru nanoparticles. These results can be important to the novel metal gate/high-k/Si MOS structure. The Ru-modified ZrHfO gate dielectric film showed a large breakdown voltage and a long lifetime. The conventional polycrystalline Si (poly-Si) charge trapping layer can be replaced by the novel floating gate structure composed of discrete nanodots embedded in the high-k film. By replacing the SiO2 layer with the ZrHfO film, promising memory functions, e.g., low programming voltage and long charge retention time, can be expected. In this study, the ZrHfO high-k MOS capacitors that separately contain nanocrystalline ruthenium oxide (nc-RuO), indium tin oxide (nc-ITO), and zinc oxide (nc-ZnO) have been successfully fabricated by the sputtering deposition method followed with the rapid thermal annealing process. Material and electrical properties of these kinds of memory devices have been investigated using analysis tools such as XPS, XRD, and HRTEM; electrical characterizations such as C-V, J-V, CVS, and frequency-dependent measurements. All capacitors showed an obvious memory window contributed by the charge trapping effect. The formation of the interface at the nc-RuO/ZrHfO and nc-ITO/ZrHfO contact regions was confirmed by the XPS spectra. Charges were deeply trapped to the bulk nanocrystal sites. However, a portion of holes were loosely trapped at the nanocrystal/ZrHfO interface. Charges trapped to the different sites lead to different detrapping characteristics. For further improving the memory functions, the dual-layer nc-ITO and -ZnO embedded ZrHfO gate dielectric stacks have been fabricated. The dual-layer embedded structure contains two vertically-separated nanocrystal layers with a higher density than the single-layer embedded structure. The critical memory functions, e.g., memory window, programming efficiency, and charge retention can be improved by using the dual-layer nanocrystals embedded floating gate structure. This kind of gate dielectric stack is vital for the next-generation nonvolatile memory applications.Item Novel 3-D IC technology(2014-05) Zhai, Yujia; Banerjee, Sanjay; Willson, C. G. (C. Grant), 1939-For many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).Item Performance of a mobile solid state GPS linked pulsed ring down array(2011-08) Reale, David V.; Mankowski, John J.; Bayne, Stephen B.The development of mobile Pulsed Ring Down Source (PRDS) arrays requires the ability to accurately determine the relative positions of array elements at distances, and in situations, where discrete measurements are not practical. At the frequencies of interest, centimeter level accuracy is required for the array to localize radiated energy at a given target location. Global Positioning System (GPS) devices and techniques are evaluated for the purpose of position acquisition. A Monte Carlo simulation was developed that takes into account the position error, the GPS timing error, and the switch jitter of the element. The error sources are combined and used a metric to evaluate and predict the array performance. Results of the GPS device testing, as well as previous work, are used as the input parameters of the simulation to determine their viability for use in the implementation of PRDS arrays. An array of low power solid state pulsed ring down sources are used to verify the results of the Monte Carlo simulations.Item Si/Ge heterojunction tunnel FETs for low power applications and junction engineering in germanium MOSFETs for high performance applications(2016-12) Hsu, William, Ph. D.; Banerjee, Sanjay; Tutuc, Emanuel; Register, Leonard F.; Lee, Jack C.; Bonnecaze, Roger T.Power dissipation has become one of the most significant impediments to continued scaling of complementary metal-oxide-semiconductor (CMOS) technology. Two approaches have been proposed for enabling supply power scaling: (i) reduction of subthreshold swing (SS) with novel operation mechanisms, and (ii) increasing of ON-current with high mobility materials or advanced device architectures. In this work, two alternative devices, tunnel field-effect transistors (TFETs) and Ge-channel MOSFETs, are being explored as possible solutions to these two approaches, respectively. TFETs have the potential to achieve a SS steeper than the thermionic emission defined limit of 60 mV/dec at room temperature to which MOSFETs are subject and, thus, enable lower voltage, lower power logic. On the other hand, Ge is promising as the enabler for high mobility channel, offering the potential to further enhance ON-current. The compatibility with conventional Si CMOS manufacturing makes Ge very attractive compared to other high mobility materials (e.g. III-V). In the first part, a Si-technology compatible Si/Ge heterojunction TFET is proposed. The device design utilizes a strained-Si/strained-Ge vertical heterojunction to provide a staggered-gap band alignment with small effective band gap and gate normal tunneling. Performance evaluation by simulation suggests that the device has the potential to be competitive with modern MOSFETs. In addition, device design guidelines in terms of electrostatic control are discussed while considering the quantum effects. In the second part, we focus on source/drain junction engineering for Ge CMOS. For n-type junctions, advanced activation scheme using non-melt sub-millisecond laser spike annealing is utilized to demonstrate excellent diffusion control and high activation level. For p-type junctions, novel BF implantation is shown to offer a higher B activation level and a shallower junction depth in Ge as compared to B and BF2 implantations. The detail diffusion mechanism of B in the presence of F is studied. High performance Ge n-type and p-type diodes are obtained along with significant reduction of contact resistance, and integration in a MOSFET process flow.Item Technology computer aided design and analysis of novel logic and memory devices(2012-08) Hasan, Mohammad Mehedi; Register, Leonard F.; Banerjee, Sanjay K.; Bank, Seth; MacDonald, Allan H.; McDermott, Mark W.Novel logic and memory device concepts are proposed and analyzed. For the latter purpose the commercial technology computer aided design (TCAD) simulators Taurus and Sentaurus Device by Synopsys are used. These simulators allow ready definition of complex device geometries. Moreover, while not all device physics models are state-of-the-art, the wide variety of device physics considered is advantageous here when not all of the critical device physics is known a priori. The initial device concept analyzed was a one transistor (1T), one capacitor (1C) – pseudo-static random access memory (SRAM). Simulations indicate that tri-gate pass-transistors will offer better gate control and reduced leakage, and tri-gate capacitors will offer increased capacitance, making the overall device performance comparable to SRAM. The second device analyzed was a quantum dot non-volatile memory. In principle, such memories become more reliable for a given tunnel oxide thickness by localizing any leaks to individual dots. However, simulations illustrate limits on dot packing density to retain this advantage due to inter-dot tunneling. The final device, proposed and extensively analyzed here, is a novel tunnel field-effect transistor (TFET), the “hetero-barrier TFET” (HetTFET). In complementary metal-oxide-semiconductor (CMOS) logic, while switching power decreases with voltages, standby power increases due to thermionic emission of charge carriers over the source-to-channel barrier in the constituent metal-oxide-semiconductor field-effect transistors (MOSFETs). As a result, CMOS voltage and, thus, power scaling is approaching an impasse. Because TFETs are not subject to thermionic emission, they are being considering as a replacement for MOSFETs. Various materials systems and device geometries have been considered. However, even in simulation, balancing switching and standby power at low voltages while still providing sufficient transconductance for rapid switching has not proven straightforward. HetTFETs are intended to achieve high on-to-off current ratios via a threshold defined by the onset of band overlap, and high ON-state transconductances via tunneling through thin barriers defined by crystal growth, rather than relying on gate-controlled barrier narrowing in whole or part for either purpose as with other designs. Simulations of n and p-channel HetTFETs suggest the possibility of current CMOS-like performance at much lower voltages.Item Zirconium-doped tantalum oxide high-k gate dielectric films(Texas A&M University, 2005-02-17) Tewg, Jun-YenA new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include the gate dielectric layer for the next generation metal-oxide-semiconductor field effect transistor (MOSFET). Due to the aggressive device scaling in ultra-large-scale integrated circuitry (ULSI), the ultra-thin conventional gate oxide (SiO2) is unacceptable for many practical reasons. By replacing the SiO2 layer with a high dielectric constant material (high-k), many of the problems can be solved. In this study, a novel high-k dielectric thin film, i.e., TaOx doped with Zr, was deposited and studied. The film?s electrical, chemical, and structural properties were investigated experimentally. The Zr dopant concentration and the thermal treatment condition were studied with respect to gas composition, pressure, temperature, and annealing time. Interface layer formation and properties were studied with or without an inserted thin tantalum nitride (TaNx) layer. The gate electrode material influence on the dielectric properties was also investigated. Four types of gate materials, i.e., aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), and tungsten nitride (WN), were used in this study. The films were analyzed with ESCA, XRD, SIMS, and TEM. Films were made into MOS capacitors and characterized using I-V and C-V curves. Many promising results were obtained using this kind of high-k film. It is potentially applicable to future MOS devices.