Browsing by Subject "Low voltage integrated circuits"
Now showing 1 - 5 of 5
Results Per Page
Sort Options
Item Class-F RF power amplifiers using coplanar waveguides for wireless communications(Texas Tech University, 2003-12) Adiraju, Lakshmikanth S.Not availableItem Dynamic CMOS circuit power dissipation methodology in low power high bandwidth chip design(2004-05) Jeong, Taikyeong, 1969-; Ambler, TonyIn a Power Efficiency System (PES), Energy Aware Computing (EAC) is a qualitative system attribute that is quantified through specific measures at the same time. In this dissertation, a low power dynamic CMOS circuit for a power dissipation methodology will be considered as a high bandwidth communication chip design. Dynamic CMOS high performance chips and system design in Hierarchical Power Efficiency System (HPES) will be considered for high bandwidth communications while low power consumption and high speed are major design goals in the VLSI design area. In order to improve the power vs. bandwidth tradeoff, it is necessary to consider digital power dissipation methodologies and power reduction techniques. Based on experiments, we are maximizing the performance of a chip taking into account delay and power. This dissertation describes the behavior of the power dissipation tradeoff between performance and energy with dynamic and static power consumption in low power high bandwidth CMOS circuits. It also discusses a novel approach of Dynamic Multi-Threshold (DMT) logic in static power consumption. The results of computer simulations of these circuits are compared and possible improvements and applications are discussed.Item Low power/low voltage LVDS (low voltage differential signal) receiver design(Texas Tech University, 2001-08) McCormick, Michael DThe focus of this thesis is to investigate the application of low-voltage/low-power design to an LVDS (Low Power Differential Signal) receiver. The power consumption and necessary source voltage levels in current CMOS circuits is dependent on the size of the transistors used and the design topology utilized to realize the circuit. A CMOS process design solution is desired to reduce the power consumption and source voltage of an LVDS receiver while maintaining full speed operation to improve overall receiver efficiency and lower receiver operating voltage from 3.3V to 1.8V. Testing and optimizing of the design of the low-power/low-voltage LVDS receiver is done through simulation and measurement of various parameters on Pspice. Tradeoffs in low-power/low-voltage circuit design are presented and investigated to determine a solution for real world application.Item Minimum supply voltage outlier analysis of large scale CMOS devices(Texas Tech University, 2004-05) McDonald, DavidThe theory and experiment of low voltage testing outlier screening methods will be proposed in this paper. Including an active study of maximum operating frequencies in comparison to their minimum voltage operating conditions. The objective of this paper is to discuss the possibility of using low voltage testing and outlier screening methods to reduce bum in time of large scale Integrated Circuits (IC's). In today's ever growing semiconductor market the need for test time reduction and test cost is ever present. By decreasing test overhead a company has the ability to lower product cost and manufacturing time and at the same time increasing potential profit and revenue.Item Switching output stages for direct PCM-PWM amplification with enhanced PSRR and THD performance(Texas Tech University, 2003-12) Pate, Michael ScotThis thesis describes the process involved in designing the loop filter that is required when changing a class-D power output stage from a full-bridge configuration to a half-bridge. The loop filter designed is part of an error correction feedback network. This thesis covers the basic theoretical derivations for the device, complete circuit design and simulation and basic device layout considerations. Ideas for future versions are given for reference.