Browsing by Subject "Logic-in-memory"
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Item Memristor based arithmetic circuit design(2016-12) Revanna, Nagaraja; Swartzlander, Earl E., Jr., 1945-; Valvano, Jonathan; Akinwande, Deji; Gerstlauer, Andreas; Schulte, MichaelThe revolution in electronics enabled by Moore’s Law has been driven historically by the ability to fabricate ever smaller features lithographically on planar semiconductor platforms. In recent years, this has been slowing down due to the myriad of problems in short channel CMOS technologies. Research is now focusing on realizing Moore’s law by architectural innovation, involving novel circuits and computation paradigms. There has been intense interest and activity directed towards designing logic circuits with memory elements. This is mainly driven by ideas like in-memory compute where logic operations are performed at the memory location in order to overcome the memory-wall bottleneck. Resistive-switching random-access memory (RRAM)/ memristors has a great potential to be the future of non-volatile memory owing to its CMOS compatibility, read-write endurance, power and speed. We describe novel high speed logic circuits for adders and multipliers built with RRAM to support the concept of logic-in-memory. These circuits have significant speed/area/power improvements over the existing designs. The complexity involved in computation in terms of controlling the basic gates, sequence of operations etc. has been significantly reduced. RRAM properties are exploited with the help of a well-known analog element called current mirror. Previously known logic-implication technique to realize digital gates comes with a serious limitation of limited fan-out. By using current mirrors, this limitation can be overcome, enabling more logic operations to run in parallel. Results show that the delay for even an XOR operation can be reduced to 1 cycle, compared to the 5 cycles taken by logic implication. Spice simulations are done with known RRAM models. Simulation results show significant improvement in power consumed over the existing designs. The design of different adders and multipliers are also described. Metrics like area, power and latency are compared, and it shows significant improvement over the state-of-the-art.Item Memristor-based arithmetic units(2016-12) Guckert, Lauren Elise; Swartzlander, Earl E., Jr., 1945-; John, Lizy; Schulte, Michael; Touba, Nur; Lee, JackThe modern computer architecture community is continually pushing the limits of performance, speed, and efficiency. Recently, the ability to satisfy this endeavor with popular CMOS technology has proved difficult, and in many settings, impossible. The community has begun to explore alternatives to standard practices, researching new components such as nanoscale structures. Additional research has applied these new components and their characteristics to rethink the architecture of the latest technology, moving away from the Von Neumann architecture. A leading technology in this effort is the memristor. Memristors are a new class of circuit elements that have the ability to change their resistance value while retaining knowledge of their current and past resistances. Their small form factor, high density, and fast switching times have sparked research in their applications in modern memory hierarchies. However, their utility in arithmetic has been minimally explored. This dissertation describes the prior work in the exploration of memristor technology, fabrication, modeling, and application, followed by the completed research performed in the design and implementation of arithmetic units using memristors. Implementations of popular adders, multipliers, and dividers in the context of memristors are designed using four approaches: IMPLY, hybrid-CMOS, threshold gates, and MAD gates. Each of these approaches has different tradeoffs and benefits for memristor-based design. Although the first three approaches have been defined in prior work, MAD gates are a novel application for memristors proposed that offer lower power, area, and delay as compared to prior approaches. This work explores these benefits for arithmetic unit design. The details of each designs, simulation results, and analyses in terms of complexity and delay and power are presented. For arithmetic units which have been designed or presented in prior work, this research improves upon the design in each metric. Many of the designs are transformed and pipelined to leverage memristor characteristics and the various approaches rather than traditional CMOS and this is discussed in detail. Overall, the proposed designs offer significant improvements to traditional CMOS designs, motivating the effort to continue exploring memristors and their application to modern computer architecture design.