Browsing by Subject "LDPC"
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Item A class of non-binary LDPC codes(Texas A&M University, 2004-09-30) Gilra, DeepakIn this thesis we study Low Density Parity Check (LDPC) and LDPC like codes over non-binary fields. We extend the concepts used for non-binary LDPC codes to generalize Product Accumulate (PA) codes to non-binary fields. We present simulation results that show that PA codes over GF(4) performs considerably better than binary PA codes at smaller block lengths and slightly better at large block lengths. We also propose a trellis based decoding algorithm to decode PA codes and show that its complexity is considerably lower than the message-passing algorithm. In the second part of the thesis we study the convergence properties of non-binary PA codes and non-binary LDPC codes. We use EXIT-charts to study the convergence properties of non-binary LDPC codes with different mean column weights and show why certain irregularities are better. Although the convergence threshold predicted by EXIT-charts on non-binary LDPC codes is quite optimistic we can still use EXIT-charts for comparison between non-binary LDPC codes with different mean column weights.Item Capacity estimation and code design principles for continuous phase modulation (CPM)(Texas A&M University, 2004-09-30) Ganesan, AravindContinuous Phase Modulation is a popular digital modulation scheme for systems which have tight spectral efficiency and Peak-to-Average ratio (PAR) constraints. In this thesis we propose a method of estimating the capacity for a Continuous Phase Modulation (CPM) system and also describe techniques for design of codes for this system. We note that the CPM modulator can be decomposed into a trellis code followed by a memoryless modulator. This decomposition enables us to perform iterative demodulation of the signal and improve the performance of the system. Thus we have the option of either performing iterative demodulation, where the channel decoder and the demodulator are invoked in an iterative fashion, or a non-iterative demodulation, where the demodulation is performed only once followed by the decoding of the message. We highlight the recent results in the estimation of capacity for channels with memory and apply it to a CPM system. We estimate two different types of capacity of the CPM system over an Additive White Gaussian Noise (AWGN). The first capacity assumes that optimum demodulation and decoding is done, and the second one assumes that the demodulation is done only once. Having obtained the capacity of the system we try to approach this capacity by designing outer codes matched to the CPM system. We utilized LDPC codes, since they can be designed to perform very close to capacity limit of the system. The design complexity for LDPC codes can be reduced by assuming that the input to the decoder is Gaussian distributed. We explore three different ways of approximating the CPM demodulator output to a Gaussian distribution and use it to design LDPC codes for a Bit Interleaved Coded Modulation (BICM) system. Finally we describe the design of Multi Level Codes (MLC) for CPM systems using the capacity matching rule.Item Code design for erasure channels with limited or noisy feedback(2009-05-15) Nagasubramanian, KarthikThe availability of feedback in communication channels can significantly increase the reliability of transmission while decreasing the encoding and decoding complexity. Most of the applications like cellular telephony, satellite communications and internet involve two-way transmission. Hence, it is important to devise coding schemes which utilize the advantages of feedback. Most of the results in code designs, which make use of feedback, concentrate on noiseless and instantaneous feedback. But in real-time systems, the feedback is usually noisy, and is available at the transmitter after some delay. Hence, it is important that we characterize the gains obtained in this case over that of one-way channels. We consider binary erasure channels to keep the problem tractable. For the erasure channels with noisy feedback, we have designed and analyzed a concatenated coding scheme, which achieves lower probability of error than any forward error correcting code of the same rate. Hence, it is shown that even noisy feedback can be useful in increasing the reliability of the channel. We have designed and analyzed a coding scheme using Low Density Parity Check (LDPC) codes along with selective retransmission strategy, which utilizes the limited (but noiseless), delayed feedback to achieve low frame error rates even with small blocklengths, at rates close to capacity. Furthermore, our scheme provides a way to trade off feedback bandwidth for reliability. The complexity of this scheme is lower than that of a forward error correcting code (FEC) of same blocklength and comparable performance. We have shown that our scheme performs better than the Automatic Repeat Request (ARQ) protocol which makes use of 1 bit feedback to signal retransmissions. For fair comparisons, we have also incorporated the rate loss due to the bits which are fed back in addition to the retransmitted bits. Thus, we have shown that for two-way communications with complexity and delay constraints, it is better to utilize the availability of feedback than to use just FEC.Item Code optimization and analysis for multiple-input and multiple-output communication systems(Texas A&M University, 2005-11-01) Yue, GuosenDesign and analysis of random-like codes for various multiple-input and multiple-output communication systems are addressed in this work. Random-like codes have drawn significant interest because they offer capacity-achieving performance. We first consider the analysis and design of low-density parity-check (LDPC) codes for turbo multiuser detection in multipath CDMA channels. We develop techniques for computing the probability density function (pdf) of the extrinsic messages at the output of the soft-input soft-output (SISO) multiuser detectors as a function of the pdf of input extrinsic messages, user spreading codes, channel impulse responses, and signal-to-noise ratios. Using these techniques, we are able to accurately compute the thresholds for LDPC codes and design good irregular LDPC codes. We then apply the tools of density evolution with mixture Gaussian approximations to optimize irregular LDPC codes and to compute minimum operational signal-to-noise ratios for ergodic MIMO OFDM channels. In particular, the optimization is done for various MIMO OFDM system configurations which include different number of antennas, different channel models and different demodulation schemes. We also study the coding-spreading tradeoff in LDPC coded CDMA systems employing multiuser joint decoding. We solve the coding-spreading optimization based on the extrinsic information SNR evolution curves for the SISO multiuser detectors and the SISO LDPC decoders. Both single-cell and multi-cell scenarios will be considered. For each of these cases, we will characterize the extrinsic information for both finite-size systems and the so-called large systems where asymptotic performance results must be evoked. Finally, we consider the design optimization of irregular repeat accumulate (IRA) codes for MIMO communication systems employing iterative receivers. We present the density evolution-based procedure with Gaussian approximation for optimizing the IRA code ensemble. We adopt an approximation method based on linear programming to design an IRA code with the extrinsic information transfer (EXIT) chart matched to that of the soft MIMO demodulator.Item Design and analysis of iteratively decodable codes for ISI channels(Texas A&M University, 2005-11-01) Doan, Dung NgocRecent advancements in iterative processing have allowed communication systems to perform close to capacity limits withmanageable complexity.For manychannels such as the AWGN and flat fading channels, codes that perform only a fraction of a dB from the capacity have been designed in the literature. In this dissertation, we will focus on the design and analysis of near-capacity achieving codes for another important class of channels, namely inter-symbol interference (ISI)channels. We propose various coding schemes such as low-density parity-check (LDPC) codes, parallel and serial concatenations for ISI channels when there is no spectral shaping used at the transmitter. The design and analysis techniques use the idea of extrinsic information transfer (EXIT) function matching and provide insights into the performance of different codes and receiver structures. We then present a coding scheme which is the concatenation of an LDPC code with a spectral shaping block code designed to be matched to the channel??s spectrum. We will discuss how to design the shaping code and the outer LDPC code. We will show that spectral shaping matched codes can be used for the parallel concatenation to achieve near capacity performance. We will also discuss the capacity of multiple antenna ISI channels. We study the effects of transmitter and receiver diversities and noisy channel state information on channel capacity.Item Error correction codes in NAND flash memory(2015-12) Regulapati, Varsha; Touba, Nur A.; Swartzlander, EarlError Correction Codes (ECC) are used in NAND Flash memories to detect and correct bit-errors. With shrinking technology nodes and increased memory complexity, bit error rates continue to grow. With mainstream usage of MLC/TLC devices where 2 or 3 bits of data are stored in each Floating-Gate transistor, this issue has become even more critical, and to address this, strong ECC schemes are being implemented. ECC is a good way to recover the wrong value from the remaining good bits, and robust error correction codes ensure data integrity. This work discusses the operation of Floating-Gate transistors and NAND Flash memory. Various causes of bit-errors in these memories such as Read Disturb, repeated Program/Erase cycles and Program Disturb are presented. Analysis of various ECC schemes such as Hamming Codes, Bose, Chaudhuri, and Hocquenghem (BCH) codes and Reed-Solomon codes and their implementation in NAND Flash memory is examined. The encoding-decoding algorithms of these codes, as well as their performance and suitability for different types of Flash technology are discussed. Special emphasis is given to the discussion on Low Density Parity Codes (LDPC), which is increasingly being used as an ECC mechanism in today’s NAND Flash devices.Item High throughput low power decoder architectures for low density parity check codes(Texas A&M University, 2005-11-01) Selvarathinam, Anand ManivannanA high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the scalable architecture and its complexity is high with higher M. The proposed tiling approach is applied to the scalable architecture to simplify the switch logic and reduce gate complexity. The tiling approach generates patterns that are used to construct the H matrix by repeating a fixed number of those generated patterns. The advantages of the proposed approach are two-fold. First, the information stored about the H matrix is reduced by onethird. Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the H matrix. Scalable architecture and tiling approach are proposed at the architectural level of the LDPC decoder. We propose two low power decoding schemes that take advantage of the distribution of errors in the received packets. Both schemes use a hard iteration after a fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a parity checker cHT that computes the number of parity checks in error. Based on cHT value, the decoder decides on performing either soft iterations or a hard iteration. The advantage of the hard iteration is so significant that the second low power scheme performs a fixed number of iterations followed by a hard iteration. To compensate the bit error rate performance, the number of soft iterations in this case is higher than that of those performed before cHT in the first scheme.Item LDPC code-based bandwidth efficient coding schemes for wireless communications(2009-06-02) Sankar, HariThis dissertation deals with the design of bandwidth-efficient coding schemes with Low-Density Parity-Check (LDPC) for reliable wireless communications. Code design for wireless channels roughly falls into three categories: (1) when channel state information (CSI) is known only to the receiver (2) more practical case of partial CSI at the receiver when the channel has to be estimated (3) when CSI is known to the receiver as well as the transmitter. We consider coding schemes for all the above categories. For the first scenario, we describe a bandwidth efficient scheme which uses highorder constellations such as QAM over both AWGN as well as fading channels. We propose a simple design with LDPC codes which combines the good properties of Multi-level Coding (MLC) and bit-interleaved coded-modulation (BICM) schemes. Through simulations, we show that the proposed scheme performs better than MLC for short-medium lengths on AWGN and block-fading channels. For the first case, we also characterize the rate-diversity tradeoff of MIMO-OFDM and SISO-OFDM systems. We design optimal coding schemes which achieve this tradeoff when transmission is from a constrained constellation. Through simulations, we show that with a sub-optimal iterative decoder, the performance of this coding scheme is very close to the optimal limit for MIMO (flat quasi-static fading), MIMO-OFDM and SISO OFDM systems. For the second case, we design non-systematic Irregular Repeat Accumulate (IRA) codes, which are a special class of LDPC codes, for Inter-Symbol Interference (ISI) fading channels when CSI is estimated at the receiver. We use Orthogonal Frequency Division Multiplexing (OFDM) to convert the ISI fading channel into parallel flat fading subchannels. We use a simple receiver structure that performs iterative channel estimation and decoding and use non-systematic IRA codes that are optimized for this receiver. This combination is shown to perform very close to a receiver with perfect CSI and is also shown to be robust to change in the number of channel taps and Doppler. For the third case, we look at bandwidth efficient schemes for fading channels that perform close to capacity when the channel state information is known at the transmitter as well as the receiver. Schemes that achieve capacity with a Gaussian codebook for the above system are already known but not for constrained constellations. We derive the near-optimum scheme to achieve capacity with constrained constellations and then propose coding schemes which perform close to capacity. Through linear transformations, a MIMO system can be converted into non-interfering parallel subchannels and we further extend the proposed coding schemes to the MIMO case too.Item Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling(2009-05-15) Wang, WeihuangThis thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels and general AWGN channels. A model of a memory-efficient low-power high-throughput multi-rate array LDPC decoder as well as its FPGA implementa- tion results is first presented. Then, I propose a decoding scheme that provides the feature of constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage levels; thereby energy use is minimized. This is in contrast to the conventional fixed-iteration decoding schemes that operate at a fixed voltage level regardless of the quality of data received. Analysis shows that the proposed decoding scheme is widely applicable for both two-phase message-passing (TPMP) decoding algorithm and turbo decoding message passing (TDMP) decoding algorithm in block fading channels, and it is independent of the specific LDPC decoder architecture. A decoder architecture utilizing our recently published multi-rate decoding architecture for general AWGN channels is also presented. The result of this thesis is a decoder design scheme that provides a judicious trade-off between power consumption and coding gain.Item Nested low-density lattice codes based on non-binary LDPC codes(2010-08) Ghiya, Ankit; Vishwanath, Sriram; Sanghvi, SujayA family of low-density lattice codes (LDLC) is studied based on Construction-A for lattices. The family of Construction-A codes is already known to contain a large capacity-achieving subset. Parallels are drawn between coset non-binary low-density parity-check (LDPC) codes and nested low-density Construction-A lattices codes. Most of the related research in LDPC domain assumes optimal power allocation to encoded codeword. The source coding problem of mapping message to power optimal codeword for any LDPC code is in general, NP-hard. In this thesis, we present a novel method for encoding and decoding lattice based on non-binary LDPC codes using message-passing algorithms.