Browsing by Subject "Integrated circuits--Design and construction"
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Item Design of radix 4 divirs using high redundancy in 65 nanometer CMOS technology(2005) Pham, Tung Nang; Swartzlander, Earl E.As technology keeps changing, there is a need to explore different design tradeoffs and alternatives. In the old technologies where die area is very important and transistors are slow, it would make sense to avoid an adder for quotient conversion and speed up division by doing on-the-fly conversion – as found in radix 4 minimally redundant dividers. By the same token, in a new technology where many millions of transistors are available in a relatively small silicon area, it is beneficial to use an adder and high degree of redundancy to simplify quotient selection and conversion. A number of radix 4 maximally redundant and overredundant dividers are designed and implemented in 65 nm CMOS technology using an ASIC flow and triple VT devices. The results show that clock and data gating saves up to ~30% power with a minimal area and timing overhead. The results also show that the radix 4 maximally redundant dividers outperform the radix 4 overredundant dividers. One design of the radix 4 maximally redundant dividers operates at a cycle time of ~1.9 ns and consumes ~5 mW of power and ~19 µW of leakage power. For a double precision division, it has a latency of ~55 ns and spends ~290 pJ of energy.Item Design, fabrication, and analysis of enhanced mobility silicon germanium transistors(2001-08) Kim, Taehoon; Banerjee, SanjayItem Implementation and qualification of a prototype tester for reflow soldering process compatability evaluation of surface mount technology components(2002-12) Wong, Anthony Yin-bong; Flake, Robert H.Item Interconnect-centric design issues in nanometer IC technology(2004-05) Shao, Muzhou, 1970-; Mok, Aloysius Ka-Lau; Wong, D. F.Item Inverse design and control of thermal systems(2002) Ertürk, Hakan; Howell, John R.Item Parametric testing, characterization and reliability of integrated circuits(2006) Datta, Ramyanshu; Abraham, Jacob A.Item Step and flash imprint lithography : materials and applications for the manufacture of advanced integrated circuits(2008-05) Palmieri, Frank Louis, 1980-; Willson, C. G.(C. Grant), 1939-Step-Flash Imprint Lithography (S-FIL[trademark]) is a low-cost, high-resolution, high-throughput pattern replication process with the potential to become the savior for the future of integrated circuit (IC) manufacturing where continued success ultimately depends on improvements in lithographic resolution. Traditional, optical lithography has driven projection imaging to its physical limits, and a new, disruptive lithography technique is needed for continued growth of the semiconductor industry. The revolutionary S-FIL process is based on the fast, in-situ polymerization of a liquid imprint material in contact with a high-resolution mold or template. The templates, fabricated by direct-write lithography, present the greatest expense when implementing an S-FIL process in manufacturing; therefore, the template lifetime must be maximized to distribute costs over a large number of products. Degradable cross-linking materials allow imprint resist contaminated templates to be cleaned without the risk of inorganic residues becoming lodged on the template surface. Cured imprint resist is insoluble in all non-reactive solvents due to its highly cross-linked structure. A polymer contaminate may be rendered soluble by degrading the cross-links and reducing the molecular weight. Several degradable cross-linker candidates were examined for compatibility with S-FIL processing and utility for wafer imprint reworking and template cleaning. The properties of the imprint resists formulated with degradable cross-linkers are reported. Tertiary ester and acetal containing moieties were di-functionalized with acrylate groups to form S-FIL compatible and acid degradable imprint precursors. Both ester and acetal cross-linkers are neat, low-viscosity ([less than or equal to] 20 cP) liquids at room temperature and are miscible with common imprint precursor components. Classical gel theory predicts that greater than 99% de-cross-linking reaction conversion is necessary to achieve solubility in a cured imprint resist formulation with 10 wt% degradable cross-linker. Concentrated sulfuric acid and heat was used to successfully strip tertiary ester cross-linkers from wafer and model template surfaces. Acetal cross-linkers were demonstrated to strip in the presence of trifluoroacetic acid at room temperature. Three-dimensional patterning is an integral benefit of S-FIL, which enables the streamlining of dual damascene processing with the use of multi-level templates. Multi-level imprint patterning allows the removal of over 100 unit process steps from the fabrication of interconnect structures in a modern IC chip. Multi-level S-FIL can be integrated into existing copper damascene interconnect fabrication using two different strategies. One technique requires an imprint resist and etch process for transferring multi-level imprints into an industry standard low-k dielectric. Some of the considerations for designing the multi-level resist and etch process are briefly described. The second strategy leverages the broad variety and flexibility of the imprint materials set, which is not available in photoresist materials technology. New “functional” imprint materials may be used with multi-level S-FIL to produce interconnect structures by directly imprinting an interlayer dielectric (ILD) precursor. The challenges associated with introducing new dielectric materials into a copper damascene process are presented. The design, processing, characterization and integration of novel materials is documented. Multi-level S-FIL with a directly patternable dielectric (DPD) enables low-cost fabrication of interconnect structures in an IC manufacturing back end of line. DPD’s based on either sol-gel or benzocyclobutane and acrylate functionalized polyhedral oligomeric silsesquioxanes show promise for integration as ILD’s based on sufficient thermal and mechanical properties. Electrical test vehicle integration with sol-gel formulated DPD’s shows promising yield of interconnect structures with vias ranging from 2 to 0.12 [mu]m. Examination of interconnect structure revealed an acceptable via profile and sufficient contact with metal one for integration in IC devices.Item Surface and interfacial chemistry of high-k dielectric and interconnect materials on silicon(2001-08) Kirsch, Paul Daniel; Ekerdt, John G.Surfaces and interfaces play a critical role in the manufacture and function of silicon based integrated circuits. It is therefore reasonable to study the chemistries at these surfaces and interfaces to improve existing processes and to develop new ones. Model barium strontium titanate high-k dielectric systems have been deposited on ultrathin silicon oxynitride in ultrahigh vacuum. The resulting nanostructures are characterized with secondary ion mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS). An interfacial reaction between Ba and Sr atoms and SiOxNy was found to create silicates, BaSixOy or SrSixOy. Inclusion of N in the interfacial oxide decreased silicate formation in both Ba and Sr systems. Furthermore, inclusion of N in the interfacial oxide decreased the penetration of Ba and Sr containing species, such as silicides and silicates. Sputter deposited HfO2 was studied on nitrided and unnitrided Si(100) surfaces. XPS and SIMS were used to verify the presence of interfacial HfSixOy and estimate its relative amount on both nitrided and unnitrided samples. More HfSixOy formed without the SiNx interfacial layer. These interfacial chemistry results are then used to explain the electrical measurements obtained from metal oxide semiconductor (MOS) capacitors. MOS capacitors with interfacial SiNx exhibit reduced leakage current and increased capacitance. Lastly, surface science techniques were used to develop a processing technique for reducing thin films of copper (II) and copper (I) oxide to copper. Deuterium atoms (D*) and methyl radicals (CH3*) were shown to reduce Cu2+ and/or Cu1+ to Cu0 within 30 min at a surface temperature of 400 K under a flux of 1×1015 atoms/cm2 ·s. Temperature programmed desorption experiments suggest that oxygen leaves the surface as D2O and CO2 for the D* and CH3* treated surfaces, respectively.Item Symbolic methods in simulation-based verification(2002) Yuan, Jun; Aziz, AdnanThis dissertation conducts research in automating the design of digital hard- ware. Specifically we apply symbolic methods in simulation-based functional ver- ification. Simulation, due to its simplicity and close coupling with the electronic design process, has been the prevalent approach to checking the correctness of de- signs. However, it suffers from several drawbacks. First, simulation verifies only the portion of design behavior that is exercised by input vectors; in addition, input vector generation itself is a time-consuming and error-prone process. Both prob- lems are aggravated by the exponential growth in integrated circuit design com- plexity. On the other side, formal verification is “vector-less” in that it certifies cor- rectness either through mathematically rigorous proofs, or by exhaustive enumera- tion of design behaviors. Needless to mention, this approach requires either enor- mous computation resources or a great deal of manual intervention to verify large designs. The problem, however, is greatly alleviated by the advent of symbolic methods, particularly the introduction of Binary Decision Diagrams to represent sets of state and transition dynamics. Symbolic formal verification has since been adopted in practice, but still limited to simple protocols and small designs. It is natural to explore ways to leverage symbolic methods in simulation verification. To this end, we introduce several such applications. We first describe what we referred to as “saturated simulation” and “retrograde analysis” in checking invariant properties that are common to electronics designs. State and transition coverage are used as the guidance for a partial symbolic simulation. Consequently, a higher level of verification confidence is achieved. We then present a symbolic input vector generation method, in which state- dependent constraints and input biases are used to confine the generated vectors to “legal” and “interesting” cases. The constraints and biases are both of a dynamic nature, that is, they can depend upon the state of the design. This enables generation of complicated sequences of vectors. We also discuss methods of optimizing the vector generation process through efficient extraction of a special kind of constraints, in which the inputs are fully specified by the state of the design. In the end, we present an alternative vector gen- eration method based on constraint synthesis. Beyond its obvious role in simulation, the method also provides a constraint based interface model for other verification approaches, such as model checking and emulation.