Browsing by Subject "Integrated circuit"
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Item An on-chip independent frequency reference circuit for audio applications(2007-12) Mullins, Austin M.; Chao, Kwong S.; Dallas, Timothy E. J.A low-cost circuit for generating a fixed frequency (nominally 100 MHz) in a CMOS process is proposed with a simulated accuracy of 0:4% across a very wide temperature range and worst-case phase noise less than -130 dBc/Hz at a 384kHz oset, making it a viable clock source for high-performance digital audio processors. The primary application of this device is to replace expensive crystal oscillators for audio processors that receive only marginal benefit from the extremely high quality of crystal-based references. A number of implementation options were considered and evaluated based on manufacturing cost, absolute accuracy, phase noise, and power consumption, taking into account the fact that automated testing facilities in industry allow manufacturers to calibrate each device after packaging. The topology chosen was a high-frequency LC-oscillator that uses an on-chip spiral inductor in conjunction with an on-chip capacitor bank and temperature compensator to produce a resonant frequency around 1.6 GHz. The output from this core LC-oscillator is then passed through a modulo-16 frequency divider chain, reducing the center frequency to 100 MHz. A circuit model was developed and this circuit was in turn laid out, veried, and extracted in software to determine the eects of anticipated parasitic RC elements. The nal post-layout simulation results suggest that it is possible to achieve 0:4% absolute accuracy after calibration, and that the circuit shows excellent phase noise performance at all simulated process corners.Item Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic(2013-03-19) Jeon, Hyung-JoonAs the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth with limited resources of channels and semiconductor devices. This trend requires designers? relentless effort for innovations. The innovations are required not only at system level but also at sub-system and circuit level. This dissertation discusses two important topics regarding high speed serial links: Clock and Data Recovery (CDR) and Current Mode Logic (CML). This dissertation proposes a mixed-mode adaptive loop gain Bang-Bang CDR. The proposed CDR enhances jitter performances even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of the Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode-based Charge Pump (CP) is proposed to minimize CP latency. The effectiveness of the proposed techniques was experimentally demonstrated by various jitter performance tests. This dissertation also presents a process-variation-resilient CML. A typical CML requires over-design to meet the specification over the wide range of process parameter variations. To address this issue, the proposed CML employs a time-reference-based adaptive biasing chain with replica load. It adjusts a variable load resistor to simultaneously regulate time-constant, voltage swing, level-shifting and DC gain. The performance of the high speed building blocks such as Bang-Bang Phase Detectors, frequency dividers and PRBS generators can be more accurately regulated with the proposed CML approach. The prototype is fabricated to experimentally compare the process-variation-induced performance degradation between the conventional and the proposed CML. Compared to the conventional CML, the proposed architecture significantly reduces the performance degradation on divider self-oscillation frequency, PRBS generator speed and PRBS output jitters over the process-variation with only <3% additional power dissipation.Item Multiple personality integrated circuits and the cost of programmability(2011-05) York, Johnathan Andrew; Chiou, Derek; Evans, Brian; Chase, Craig; Gaussiran, Thomas; Pan, David; Pingali, KeshavThis dissertation explores the cost of programmability in computing devices as measured relative to fixed-function devices implementing the same functionality using the same physical fabrication technology. The central claim elevates programmability to an explicit design parameter that (1) can be rigorously defined, (2) has measurable costs amenable to high-level modeling, (3) yields a design-space with distinct regions and properties, and (4) can be usefully manipulated using computer-aided design tools. The first portion of the the work is devoted to laying a rigorous logical foundation to support both this and future work on the subject. The second portion supports the thesis within this established logical foundation, using a specific engineering problem as a narrative vehicle. The engineering problem explored is that of mechanically adding a useful degree of programmability into preexisting fixed-function logic while minimizing the added overhead. Varying criteria for usefulness are proposed and the relative costs estimated both analytically and through case-study using standard-cell logic synthesis. In the case study, a methodology for the automatic generation of reconfigurable logic highly optimized for a specific set of computing applications is demonstrated. The approach stands in contrast to traditional reconfigurable computing techniques which focus on providing general purpose functionality at the expense of substantial overheads relative to fixed-purpose implementations.