Browsing by Subject "Hardware"
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Item Hardware Prototyping of Two-Way Relay Systems(2012-10-19) Wu, QiongIn this thesis, I conduct the hardware prototyping of a two-way relay system using the National Instruments FlexRIO hardware platform. First of all, I develop several practical mechanisms to solve the critical synchronization issues of the systems, including Orthogonal Frequency-Division Multiplexing (OFDM) frame synchronization at the receiver, source to source node synchronization, and handshaking between the sources and relay nodes. Those synchronization methods control the behavior of the two source nodes and the relay node, which play critical roles in the two-way relay systems. Secondly, I develop a pilot-based channel estimation scheme and validate it by showing the successful self-interference cancellation for the two-way relay systems. In particular, I experiment the self-interference cancellation technique by using several channel estimation schemes to estimate both source to relay channels and relay to source channels. Moreover, I implement the physical layer of a 5 MHz OFDM scheme for the two-way relay system. Both the transmitter and receiver are designed to mimic the Long Term Evolution (LTE) downlink scenario. The physical layer of the transmitter has been implemented in Field-Programmable Gate Arrays (FPGAs) and executed on the hardware board, which provides high throughput and fundamental building blocks for the two-way relay system. The physical layer of receiver is implemented in the real-time controller, which provides the ?exibility to rapidly recon?gure the system. Finally, I demonstrate that the 5MHz OFDM based two-way relay system can achieve reliable communications, when the channel estimation and system synchronization can be correctly executed.Item RSA in hardware(2010-12) Gillmore, Brooks Colin; Abraham, Jacob A.; McDermott, MarkThis report presents the RSA encryption and decryption schemes and discusses several methods for expediting the computations required, specifically the modular exponentiation operation that is required for RSA. A hardware implementation of the CIOS (Coarsely Integrated Operand Scanning) algorithm for modular multiplication is attempted on a XILINX Spartan3 FPGA in the TLL-5000 development platform used at the University of Texas at Austin. The development of the hardware is discussed in detail and some Verilog source code is provided for an implementation of modular multiplication. Some source code is also provided for an RSA executable to run on the TLL-6219 ARM-based development platform, to be used to generate test vectors.