Browsing by Subject "Field programmable gate arrays."
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Item Accelerating path planning algorithms with high level synthesis tools and FPGAs.(2013-05-15) Trower, John W.; Duren, Russell Walker.; Electrical and Computer Engineering.; Baylor University. Dept. of Electrical and Computer Engineering.Accelerating path planning algorithms with field programmable gate arrays (FPGA) allows the designer to achieve significant performance increases over using a traditional central processing unit (CPU). Converting an algorithm to run on an FPGA is a complicated and time consuming process. This thesis develops and verifies a design framework that demonstrates how to design a path planning algorithm in a high level language, then convert the algorithm into hardware description languages using high level synthesis tools. This design framework will be used to demonstrate the acceleration of a genetic algorithm.Item A comparison of field programmable gate arrays and digital signal processors in acoustic array processing.(2006-07-29T16:28:42Z) Stevenson, Jeremy C.; Duren, Russell Walker.; Thompson, Michael Wayne.; Engineering.; Baylor University. Dept. of Electrical and Computer Engineering.The Field Programmable Gate Array's (FPGA) constant growth in computing power has given embedded system developers a choice to replace their current processors with a FPGA. However, most systems continue to use the original processor due to familiarity and design speed. Design tools, such as Simulink for MATLAB, have created a potential for significantly reducing FPGA development time. This potential was explored by developing an acoustic array processing system on both a FPGA and a DSP (Digital Signal Processor). The system includes a filtering stage, a correlation stage, and a trigonometric math stage. All of these stages are computationally intensive which provide an accurate portrayal of the chips' capabilities. The paper documents the comparison of the FPGA and the DSP implementations in regards to the performance of each implementation, the design time of each implementation and the capability of the design tools used in each implementation.Item Evaluating Impulse C and multiple parallelism partitions for a low-cost reconfigurable computing system.(2009-04-01T12:08:36Z) Li Shen, Carmen C.; Duren, Russell Walker.; Engineering.; Baylor University. Dept. of Electrical and Computer Engineering.Impulse C is a C-to-HDL compiler from Impulse Accelerated Technology that facilitates the introduction of software programmers, mathematicians, and scientists, into the realm of FPGA-based algorithm development for high-speed numerical computation. This thesis evaluates the Impulse C programming language and explores differing levels of parallelism across multiple, homogeneous, FPGA development platforms using the Aurora serial communication scheme. Impulse C and Xilinx IP cores are employed in the numerical computation of a neural network consisting of 27 inputs and 1200 outputs. The artificial neural network is capable of emulating an underwater acoustic environment and has been used to determine characteristic parameters of reflections from the ocean floor. Timing, logic utilization and ease-of-use are metrics used to evaluate Impulse C in the automatic generation of VHDL code for the network test application. Implementations with parallelism at the system level and at the intermediate (loop) level are explored as part of this study.Item Research on board to board communication for a reconfigurable computing system.(2009-08-25T16:34:45Z) Yue, Wu, 1983-; Duren, Russell Walker.; Engineering.; Baylor University. Dept. of Electrical and Computer Engineering.Board-to-board communications are very important for interconnecting multiple FPGA boards in a reconfigurable computing cluster. Researchers at Baylor University have developed a reconfigurable computing cluster that uses the Impulse C language to provide a platform for software designers to design hardware-accelerated systems. This thesis describes the development of two Impulse C implementations for the interconnection of Xilinx FPGA boards; one using parallel and one using serial communication hardware. Impulse C is used to design a software-numerical-communication function integrated into the hardware communication system. The hardware communication protocol is designed and implemented using VHDL and Xilinx’s Embedded Development Kit (EDK). The performance of the two communication systems are tested and compared by simulation and real time hardware test applications. The advantages and disadvantages between the two different communication systems are explored as part of this research.