Browsing by Subject "Fault injection"
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Item Developing a multi-level fault injection environment(2015-05) Samynathan, Balavinayaga; Abraham, Jacob A.Dependability and fault tolerance are important aspects of modern computer systems. Particle strikes or electromagnetic interference can cause internal state of the system to change, which might cause errors to the system with non-negligible probability. Such errors are termed "soft errors". Bit flips in the design are good way to model these soft-errors. These bit-flips due to soft errors are random and transient in a design, making their analysis more difficult than simple stuck-at faults. Interestingly only a few of the flops which are affected by radiation cause soft errors, due to different propagation paths and functional impact of the flops. In order to improve the dependability of a system with reasonable overhead, the flops in a design which are most vulnerable to soft errors need to be protected. Each application case can potentially expose a slightly different set of flip-flops as vulnerable. Hence different tools are required to confidently analyse soft errors for evaluating the fault tolerance. As part of the thesis, I have developed a suite of tools for analyzing soft errors. The multi-level tools are necessary for complete fault tolerance analysis and identifying the most vulnerable flip-flops in a specific processor. The first part of the thesis describes the FPGA development framework for a specific processor. Simulation based fault injection techniques are described in the later sections. The final parts cover analysis techniques and applications that can benefit from such systems.Item Fiesta++ : a software implemented fault injection tool for transient fault injection(2014-12) Chaudhari, Ameya Suhas; Abraham, Jacob A.Computer systems, even when correctly designed, can suffer from temporary errors due to radiation particles striking the circuit or changes in the operating conditions such as the temperature or the voltage. Such transient errors can cause systems to malfunction or even crash. Fault injection is a technique used for simulating the effect of such errors on the system. Fault injection tools inject errors in either the software running on the processors or in the underlying computer hardware to simulate the effect of a fault and observe the system behavior. These tools can be used to determine the different responses of the system to such errors and estimate the probability of occurrence of errors in the computations performed by the system. They can also be used to test the fault tolerance capabilities of the system under test or any proposed technique for providing fault tolerance in circuits or software. As a part of this thesis, I have developed a software implemented fault injection tool, Fiesta++, for evaluating the fault tolerance and fault response of software applications. Software implemented fault injection tools inject faults into the software state of the application as it runs on a processor. Since such fault injection tools are used to conduct experiments on applications executing natively on a processor, the experiments can be carried out at almost the same speed as the application execution and can be run on the same hardware as used by the software application in the field. Fiesta++ offers two modes of operation: whitebox and blackbox. The whitebox mode assumes that users have some degree of knowledge of the structure of the software under test and allows them to specify fault injection targets in terms of the application variables and fault injection time in terms of code locations and events at run time. It can be used for precise fault injection to get reproducible outcomes from the fault injection experiments. The blackbox mode is targeted for the case where the user has very little or no knowledge of the application code structure. In this mode, Fiesta++ provides the user with a view of the active process memory and an array of associated information which a user can use to inject faults.Item A microprocessor performance and reliability simulation framework using the speculative functional-first methodology(2011-12) Yuan, Yi; Chiou, Derek; Erez, MattanWith the high complexity of modern day microprocessors and the slow speed of cycle-accurate simulations, architects are often unable to adequately evaluate their designs during the architectural exploration phases of chip design. This thesis presents the design and implementation of the timing partition of the cycle-accurate, microarchitecture-level SFFSim-Bear simulator. SFFSim-Bear is an implementation of the speculative functional-first (SFF) methodology, and utilizes a hybrid software-FPGA platform to accelerate simulation throughput. The timing partition, implemented in FPGA, features throughput-oriented, latency-tolerant designs to cope with the challenges of the hybrid platform. Furthermore, a fault injection framework is added to this implementation that allows designers to study the reliability aspects of their processors. The result is a simulator that is fast, accurate, flexible, and extensible.