Browsing by Subject "Electron beam lithography"
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Item Design for manufacturing with advanced lithography(2014-08) Yu, Bei; Pan, David Z.Shrinking the feature size of very large scale integrated circuits (VLSI) with advanced lithography has been a holy grail for the semiconductor industry. However, the gap between manufacturing capability and the expectation of design performance becomes critically challenged in sub-16nm technology nodes. To bridge this gap, design for manufacturing (DFM) is a must to co-optimize both design and lithography process at the same time. DFM for advanced lithography could be defined very differently under different circumstances. In general, progress in advanced lithography happens along three different directions: (1) New patterning technique (e.g., layout decomposition for different patterning techniques); (2) New design methodology (e.g., lithography aware standard cell design and physical design); (3) New illumination system (e.g., layout fracturing for EBL system, stencil planning for EBL system). In this dissertation, we present our research results on design for manufacturing (DFM) with multiple patterning lithography (MPL) and electron beam lithography (EBL) addressing these three DFM research directions in advanced lithography. For the research direction of new patterning technique, we study the layout decomposition problems for different patterning technique and explore four important topics: (1) layout decomposition for triple patterning; (2) density balanced layout decomposition for triple patterning; (3) layout decomposition for triple patterning with end-cutting; (4) layout decomposition for quadruple patterning and beyond. We present the proof that triple patterning layout decomposition is NP-hard. Besides, we propose a number of CAD optimization and integration techniques to solve different problems. For the research direction of new design methodology, we will show the limitation of traditional design flow. That is, ignoring triple patterning lithography (TPL) in early stages may limit the potential to resolve all the TPL conflicts. We propose a coherent framework, including standard cell compliance and detailed placement, to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement where the layout decomposition and placement can be resolved simultaneously. In addition, we propose a linear dynamic programming to solve TPL aware detailed placement with maximum displacement, which can achieve good trade-off in terms of runtime and performance. For the EBL illumination system, we focus on two topics to improve the throughput of the whole EBL system: (1) overlapping aware stencil planning under MCC system; (2) L-shape based layout fracturing for mask preparation. With simulations and experiments, we demonstrate the critical role and effectiveness of DFM techniques for the advanced lithography, as the semiconductor industry marches forward in the deeper sub-micron domain.Item Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects(2013-05) Wu, Zhuojie; Ho, P. S.The continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.