Browsing by Subject "Digital-to-analog converters"
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Item Design trade-off of low power continuous-time [Sigma Delta] modulators for A/D conversions(2007-12) Song, Tongyu; Yan, ShouliThe research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.Item High speed oversampled analog-to-digital conversion techniques(Texas Tech University, 1993-08) Burra, GangadharNot availableItem Improving flexibility of data acquisition modules(Texas Tech University, 2000-12) Albus, Jonathan ZacharyThe ability for customers to quickly and effectively evaluate general-purpose data converter devices is an important topic that semiconductor manufacturers must address. These systems must be simple enough to quickly and cheaply develop, while still allowing a complete evaluation platform for the target device(s). The integration of dense digital logic into the evaluation module design in the form of CPLD or FPGA technology can provide this ability. This paper documents the design of such an evaluation module, using a CPLD to implement logic control for host-less operation of multiple ADC and DAC devices. Also included is the design of a PC-to-EVM system using Visual Basic 6.0^"^, which allows the customer to evaluate the target ADC(s) using a PC interface and GUI. Each of these techniques developed for a data converter evaluation module can be used to address these same issues for a wide variety of devices.Item Oversampled multi-bit sigma-delta A/D converters(Texas Tech University, 1997-08) Kinyua, Martin K.The objective of this research is geared towards proposing sigma-delta modulators that will achieve high resolution at wide bandwidths, meaning A/D conversion at rates exceeding 1 MHz with a resolution of at least 12 bits [1, p.219]. As will become clear later, this task not only requires the use of high-order noise shaping but also multi-bit quantization. On that basis, this thesis starts with a basic sigma-delta topology which employs multi-bit quantization with single-bit feedback thus avoiding the very strict linearity requirements imposed on DAC in the feedback path of a sigma-delta loop. The concept is then further extended to develop novel sigma-delta topologies that accomplish a synergetic combination of the advantages of sigma-delta and pipeline ADCs to provide wide dynamic range at wide bandwidths, a performance which may not be currently realized using either of the structures alone. The validity of the proposed topologies is confirmed by system level simulations.