# Browsing by Subject "Delay"

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Item Analysis of Platoon Impacts on Left-Turn Delay at Unsignalized Intersections(2012-02-14) Wan, FengShow more Traffic platoons created by traffic signals may have impacts on the operations of downstream intersections because they change the arrival pattern and gap distribution of upstream traffic. There?s been a lot of research dealing with platoon effects on operations at signalized intersections, while very limited research has been done for that of unsignalized intersections. This research aims to develop a methodology for analyzing the platoon impacts on major-street left-turn (MSLT) delay at two-way stop-controlled (TWSC) intersections. The main idea is using a microscopic simulation tool to simulate different platoon scenarios in opposing through traffic, then applying regression models to capture the impacts of platoons on the delay of MSLT. Two platoon variables were adopted as a simplification of the complex platoon scenarios, making it practical to analyze the platoon effects on MSLT delay. The first two steps were to build simulation models for real-world unsignalized intersections and simulate scenarios with a combination of various factors related to platoons in VISSIM simulation. Calibrations of these simulation models based on field data were performed before simulation started. The next step was to define, derive and calibrate two platoon variables for describing the duration and intensity of platoon arrivals in the opposing through traffic, which effectively simplified the large combination of various factors. At last, the two platoon variables and their relationship with MSLT delay change factor were modeled with regression tools. A relationship between the two variables and the delay change factor was established, which indicated a positive effect by upstream platoons on MSLT delay and made it possible to quantify the impacts. The findings in this research could also be used for future research on left turn treatment regarding platoon or signal impacts.Show more Item Area, delay and power comparison of adder topologies(2015-12) Ganesan, Sarvesh; Swartzlander, Earl E., Jr., 1945-; Touba, NurShow more An adder is an indispensable component for a processing system and is ever-present on an integrated circuit. With scaling and the increasing levels of integration seen in the contemporary integrated circuits, power consumption has become an important factor in deciding the performance of any adder circuit in addition to the speed. Area has always been another factor which is taken into account based on the application. This work provides a comprehensive analysis of the standard cell based CMOS implementations of six adder topologies of different word sizes in 45nm technology. The analysis is done on leakage power, dynamic power, speed and area. The switching activities of the circuits were captured using dynamic gate level simulation to perform the time based peak power analysis. Static timing analysis was performed to estimate the delay of the critical path for each circuit. The complexity of the circuit is decided based on the number of gates used in the implementation and the area utilized by the standard cells in the circuit. The analysis and results presented in this report will be helpful in choosing a specific adder configuration for an integrated circuit based on the constraints related to its application.Show more Item Effect of varying the delay distribution in different classes of networks: random, scale-free, and small-world(2009-05-15) Jang, Bum SoonShow more Networks, and associative properties, prevalent in natural and artificial systems have been investigated extensively. A common method for network analysis is based on graph theory because graphs naturally represent the relationship between objects in a network. In this context, three classes of networks are frequently investigated: random, scale-free, and small-world network. The three classes of networks have been studied extensively, to find properties and to analyze the structure of each network type using various measurements. Despite that all real networks have time delays, researchers relying on graph theory commonly disregarded delay or considered them only as being homogeneous. Delay cannot be ignored because delay has a critical role in many types of networks, such as the internet, business networks, and biological networks. The role and effect of delay, however, are still not clearly understood in the context of graph-based analysis. Furthermore, graph-based analysis of networks containing delay has not been attempted so far. In this thesis, I compared multiple network structures with delay in a graph context. I incorporated delay information into the network topology by a simple technique called temporal augmentation. Also, I investigated the effect of varying the delay distribution in these different network classes with added delay. In this thesis, several experiments were conducted based on two network construction methods (naive, and modified conventional method) and three types of delay distributions (peaked, uniform, and unimodal), with different network parameters. From the experiments, I found that the effect of the number of hubs in scale-free network was negligible, while the role of neighborhood size in small-world networks was significant. Also, neighborhood size affect smallworldness of networks. Effect of delay was expressed differently based on different patterns of delay distribution and network structures. Networks with uniformly randomly distributed delay had the best robustness in dealing with delay. Unimodal cases had larger increases in shortest path sum than uniform case. Peaked cases showed the worst increase in shortest path sum. Also, sparse networks with high smallworldness was less affected by delay while dense networks with high smallworldness more affected by delay. These results extended understanding of the relationship between network structures and delay.Show more Item Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy(2009-05-15) Chang, SanghoanShow more The operating clock frequency is determined by the longest signal propagation delay, setup/hold time, and timing margin. These are becoming less predictable with the increasing design complexity and process miniaturization. The difficult challenge is then to ensure that a device operating at its clock frequency is error-free with quantifiable assurance. Effort at device-level engineering will not suffice for these circuits exhibiting wide process variation and heightened sensitivities to operating condition stress. Logic-level redress of this issue is a necessity and we propose a design-level remedy for this timing-uncertainty problem. The aim of the design and analysis approaches presented in this dissertation is to provide framework, SABRE, wherein an increased operating clock frequency can be achieved. The approach is a combination of analytical modeling, experimental analy- sis, hardware /time-redundancy design, exception handling and recovery techniques. Our proposed design replicates only a necessary part of the original circuit to avoid high hardware overhead as in triple-modular-redundancy (TMR). The timing-critical combinational circuit is path-wise partitioned into two sections. The combinational circuits associated with long paths are laid out without any intrusion except for the fan-out connections from the first section of the circuit to a replicated second section of the combinational circuit. Thus only the second section of the circuit is replicated. The signals fanning out from the first section are latches, and thus are far shorter than the paths spanning the entire combinational circuit. The replicated circuit is timed at a subsequent clock cycle to ascertain relaxed timing paths. This insures that the likelihood of mistiming due to stress or process variation is eliminated. During the subsequent clock cycle, the outcome of the two logically identical, yet time-interleaved, circuit outputs are compared to detect faults. When a fault is detected, the retry sig- nal is triggered and the dynamic frequency-step-down takes place before a pipe flush, and retry is issued. The significant timing overhead associated with the retry is offset by the rarity of the timing violation events. Simulation results on ISCAS Benchmark circuits show that 10% of clock frequency gain is possible with 10 to 20 % of hardware overhead of replicated timing-critical circuit.Show more Item Performance Analysis of Isolated Intersection Traffic Signals(2013-08-01) Yin, KaiShow more This dissertation analyzes two unsolved problems to fulfill the gap in the literature: (1). What is the vehicle delay and intersection capacity considering left-turn traffic at a pre-timed signal? (2). What are the mean and variance of delay to vehicles at a vehicle-actuated signal? The first part of this research evaluates the intersection performance in terms of capacity and delay at an isolated pre-timed signal intersection. Despite of a large body of literature on pre-timed signals, few work has examined the interactions be- tween left-turn and through vehicles. Usually a protected left-turn signal phase, before (leading) or after (lagging) through signal, is applied to a signalized inter- section when the traffic demand is relatively high. A common problem for leading left-turn operation is the blockage to left-turn vehicles by through traffic, particularly at an intersection with a short left-turn bay. During the peak hour, some vehicles on the through lane might not be able to depart at the end of a cycle, resulting in an increased probability of left-turn blockage. In turn, the blocked left-turn vehicles may also delay the through traffic to enter the intersection during the following cycle. Those problems may not exist for a lagging left-turn operation, since left-turn vehicles intend to spill out of the bay under heavy traffic. In this case, the through capacity is reduced, leading to an increase of total delay. All of these factors contribute to the difficulties of estimating the delay and capacity for an isolated intersection. In order to examine this missing part of study on the signalized intersection, two probabilistic models are proposed to deal with the left-turn bay blockage and queue spillback in a heuristic manner. Numerical case studies are also provided to test the proposed models. The second part of this research studies an isolated intersection with vehicle-actuated signal. Typically an advanced detector is located at a distance prior to the intersection such that an arriving vehicle triggers a green time extension in or- der to pass through without any stop. This extended time period actuated by the vehicle is called unit extension in this study. If no vehicle actuation occurs during a unit extension, the green phase would terminate in order to clear queues in other approaches. In this way, the actuated system dynamically allocates the green time among multiple approaches according to vehicle arrivals. And the unit extension is the only control parameter in this case. We develop a model to study the vehicle delay under a general arrival distribution with a given unit extension. Our model allows optimizing the intersection performance over the unit extension. The third part of this research applies graphical methods and diffusion approximations to the traffic signal problems. We reinterpret a graphical method which is originally proposed by Newell in order to directly measure the variance of the time for the queue clearance at a signalized intersection, which remains yet to be carefully examined in practice and would be rather challenging if only using the conventional queuing techniques. Our results demonstrate that graphical method explicitly presents both the deterministic and stochastic delay. We also illustrate that the theoretical background for the graphical methods in this particular application is inherently the diffusion approximation. Furthermore, we investigate the problems of disruptions occurred during a pre-timed traffic signal cycle. By diffusion approximation, we provide quantitative estimation on the duration that the effects of disruptions would dissipate.Show more Item Quantifying the impacts of regulatory delay on housing affordability and quality in Austin, Texas(2015-05) Shannon, Megan Elizabeth; Wegmann, Jake; Mitchell, TerryShow more Regulatory delay during site plan review of multifamily projects in Austin has three primary impacts: 1) it generates unexpected development costs which increases housing prices over-time; 2) it stifles innovation and decreases quality of development; and 3) it promotes exurban growth. These impacts reduce affordability and quality of life for all Austinites and thwart the goals of the Imagine Austin comprehensive plan. As regulatory delays have increased remarkably since 2009, strong rent growth has compensated for this growing uncertainty throughout the Austin market. If regulatory delays are eliminated and developers receive approvals for multifamily projects within the 120 day mandate instead of the 223 day average, renters could see relief of 4-5% on their rent, or an average of $60 per month or $720 annually in Central Austin. Interviews with 14 Austin-area residential developers confirm these delays, costs, and impacts on their projects. On average it takes 3.5 additional months to receive site plan approvals in Austin in addition to the code mandated four month cycle. Austin's peer cities fare differently. The average delay in Denver, Colorado is three weeks, and is just several days in Raleigh, North Carolina. Whereas land use regulations theoretically generate positive externalities, delays in administering those regulations generate no benefits to the community. During this unforeseen 3.5 months, developers accrue unexpected costs such as legal fees, and developer overhead which includes the opportunity costs of not pursuing other deals. Construction costs increase during delays, and developers must continue to pay for land options and carry costs. In the short-term, developers pay for these unexpected costs out-of-pocket, and by reducing construction costs, which can result in lower quality materials or amenities. Unexpected costs roll into the project's overall budget, resulting in more expensive development projects. More expensive projects require higher rents in order to maintain the development team's expected yield on cost. Further, interviews with urban designers and civil engineers reveal that regulatory delay stifles private sector innovation in the built environment. Developer interviews and case studies suggest that regulatory delay promotes exurban growth instead of urban infill in the Austin metropolitan area.Show more Item Robustness properties of quaternion-based attitude control systems(2016-05) Yang, Sungpil; Akella, Maruthi Ram, 1972-; Bakolas, Efstathios; Arapostathis, Aristotle; Acikmese, Behcet; Mazenc, FredericShow more Both stabilizing and tracking solutions of the rigid-body attitude control problem, using various attitude representations, are now well understood. Based on the sensor availability, numerous full-state feedback or gyro-free output feedback controllers have been proposed and studied. In the dissertation, we revisit classical proportional-derivative (PD) type attitude controllers when the system is subject to uncertainties like time-delay in the feedback loop, measurement errors, external disturbance torques and modeling uncertainties. We not only analyze existing PD-type controllers while considering various types of uncertainties, but also design tracking controllers robust to the system parameter uncertainties. We adopt the quaternion representation for the attitude kinematics so that we can avoid the geometric singularities coming with minimal 3-dimensional parameter representations. For stability and robustness analysis of the PD-type controllers, we do not rely on the linear system framework in which the original dynamics are considered as the sum of the nominal linear part and the nonlinear perturbation part. Instead, another approach is suggested as suitable for the quaternion kinematic representation so that results are not restricted to a neighborhood of the origin. We first deal with one of the common Lyapunov functions used for quaternion-based attitude control problem. Then, through the strictification process, a new Lyapunov function is constructed which can be analyzed based on the standard Lyapunov stability analysis method. As a result, we establish sufficient conditions for locally stability or boundedness of the system subject to aforementioned uncertainties for both PD full-state feedback and PD-like gyro-free output feedback controllers. When our scope is narrowed to the system parameter uncertainties, we propose adaptive controllers that track predefined reference trajectories and estimate the unknown inertial parameters. Specifically, we apply a dynamic scaling-based Immersion and Invariance method for the first time to the attitude tracking problem. We also provide a way to control and estimate the upper bound of a dynamic scaling factor which has not yet been seen in the literature.Show more Item Throughput and Delay Analysis in Cognitive Overlaid Networks(2011-02-22) Gao, LongShow more Consider a cognitive overlaid network (CON) that has two tiers with different priorities: a primary tier vs. a secondary tier, which is an emerging network scenario with the advancement of cognitive radio (CR) technologies. The primary tier consists of randomly distributed primary radios (PRs) of density n, which have an absolute priority to access the spectrum. The secondary tier consists of randomly distributed CRs of density m = n^y with y greater than or equal to 1, which can only access the spectrum opportunistically to limit the interference to PRs. In this dissertation, the fundamental limits of such a network are investigated in terms of the asymptotic throughput and packet delay performance when m and n approaches infinity. The following two types of CONs are considered: 1) selfish CONs, in which neither the primary tier nor the secondary tier is willing to route the packets for the other, and 2) supportive CONs, in which the secondary tier is willing to route the packets for the primary tier while the primary tier does not. It is shown that in selfish CONs, both tiers can achieve the same throughput and delay scaling laws as a stand-alone network. In supportive CONs, the throughput and delay scaling laws of the primary tier could be significantly improved with the aid of the secondary tier, while the secondary tier can still achieve the same throughput and delay scaling laws as a stand-alone network. Finally, the throughput and packet delay of a CON with a small number of nodes are investigated. Specifically, we investigate the power and rate control schemes for multiple CR links in the same neighborhood, which operate over multiple channels (frequency bands) in the presence of PRs with a delay constraint imposed on data transmission. By further considering practical limitations in spectrum sensing, an efficient algorithm is proposed to maximize the average sum-rate of the CR links over a finite time horizon under the constraints on the CR-to-PR interference and the average transmit power for each CR link. In the proposed algorithm, the PR occupancy of each channel is modeled as a discrete-time Markov chain (DTMC). Based on such a model, a novel power and rate control strategy based on dynamic programming (DP) is derived, which is a function of the spectrum sensing output, the instantaneous channel gains for the CR links, and the remaining power budget for the CR transmitter. Simulation results show that the proposed algorithm leads to a significant performance improvement over heuristic algorithms.Show more