Browsing by Subject "Data compression (Computer science)--Testing"
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Item Low power scan testing and test data compression(2006) Lee, Jinkyu; Touba, Nur A.As the size and complexity of systems-on-a-chips (SOCs) continue to grow, test data volume and test power consumption have increased dramatically. A large amount of test data causes long test time and a large memory requirement on the tester. Large power consumption during test can result in high packaging cost and Vdd drop/ground bounce problems. In this dissertation, five techniques for reducing test data volume, test power consumption, or both, are proposed. The first is a new encoding algorithm that can be used in conjunction with any LFSR reseeding scheme to significantly reduce power consumption during test. The second is a scheme for inserting a linear feedforward network composed of XOR gates in the scan chains to reduce power consumption during test by reducing the number of scan shift cycles. The third is a built-in self-test (BIST) scheme that both reduces overhead for detecting random-patternresistant (r.p.r.) faults as well as reduces power consumption during test. The fourth is a technique for improving the compression achieved with any linear decompressor by adding a small non-linear decoder that exploits bit.Item New approaches and limits to test data compression for systems-on-chip(2004) Balakrishnan, Kedarnath Jayaraman; Touba, Nur A.Recent advances in design technology have made it possible to build systems containing different types of components on the same chip. These complex systems-onchip (SoC) contain components that cover a wide range of functions and technologies from processors and other digital circuits in CMOS to DRAM to analog circuits. As a result, the testing of such complex SoCs has become an important and dif- ficult problem. This thesis investigates the use of test data compression methods to deal with the enormous amount of test data of complex SoCs. The first part of this thesis studies the use of an embedded processor present in the SoC to help in testing the other cores. Specifically, the focus is on the use of processor to perform test vector decompression in software. The next part of this thesis looks at methods for improving the compression of hardware based linear decompression techniques. The last part uses entropy theory to calculate the limits to test data compression.Item Testing for delay defects utilizing test data compression techniques(2008-05) Putman, Richard Dean, 1970-; Touba, Nur A.As technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.