Browsing by Subject "DAC"
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Item DAC Linearization Techniques for Sigma-delta Modulators(2012-02-14) Godbole, AkshayDigital-to-Analog Converters (DAC) form the feedback element in sigma-delta modulators. Any non-linearity in the DAC directly degrades the linearity of the modulator at low and medium frequencies. Hence, there is a need for designing highly linear DACs when used in high performance sigma-delta modulators. In this work, the impact of current mismatch on the linearity performance (IM3 and SQNR) of a 4-bit current steering DAC is analyzed. A selective calibration technique is proposed that is aimed at reducing the area occupancy of conventional linearization circuits. A statistical element selection algorithm for linearizing DACs is proposed. Current sources within the required accuracy are selected from a large set of current sources available. As compared with existing calibration techniques, this technique achieves higher accuracy and is more robust to variations in process and temperature. In contrast to existing data weighted averaging techniques, this technique does not degrade SNR performance of the ADC. A 5th order, 500 MS/s, 20 MHz sigma-delta modulator macro-model was used to test the linearity of the DAC.Item Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters(2012-02-14) Chen, HongboNowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance.Item Tunable mismatch shaping for bandpass Delta-Sigma data converters(2011-05) Akram, Waqas; Swartzlander, Earl E.; Driga, Mircea D.; Orshansky, Michael E.; Telang, Vivek; Touba, Nur A.Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity.