Browsing by Subject "Crosstalk"
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Item Communication Reliability in Network on Chip Designs(2012-10-19) Kumar, ReeshavThe performance of low latency Network on Chip (NoC) architectures, which incorporate fast bypass paths to reduce communication latency, is limited by crosstalk induced skewing of signal transitions on link wires. As a result of crosstalk interactions between wires, signal transitions belonging to the same flit or bit vector arrive at the destination at different times and are likely to violate setup and hold time constraints for the design. This thesis proposes a two-step technique: TransSync- RecSync, to dynamically eliminate packet errors resulting from inter-bit-line transition skew. The proposed approach adds minimally to router complexity and involves no wire overhead. The actual throughput of NoC designs with asynchronous bypass designs is evaluated and the benefits of augmenting such schemes with the proposed design are studied. The TransSync, TransSync-2-lines and RecSync schemes described here are found to improve the average communication latency by 26%, 20% and 38% respectively in a 7X7 mesh NoC with asynchronous bypass channel. This work also evaluates the bit-error ratio (BER) performance of several existing crosstalk avoidance and error correcting schemes and compares them to that of the proposed schemes. Both TransSync and RecSync scheme are dynamic in nature and can be switched on and off on-the-fly. The proposed schemes can therefore be employed to impart unequal error protection (UEP) against intra-flit skewing on NoC links. In the UEP, a larger fraction of the energy budget is spent in providing protection to those parts of the data being transmitted on the link which have a higher priority, while expending smaller effort in protecting relatively less important parts of the data. This allows us to achieve the prescribed level of performance with lower levels of power. The benefits of the presented technique are illustrated using an H.264 video decoder system-on-chip (SoC) employing NoC architecture. We show that for Akyio test streams transmitted over 3mm long link wires, the power consumption can be reduced by as much as 20% at the cost of an acceptable degradation in average peak signal to noise ratio (PSNR) with UEP.Item Correlation properties of diffusers for multiplex holography(Texas Tech University, 1979-08) Kral, Edward LeeA promising method of representing two-dimensional space-variant optical systems is through multiplex holography. The multiplexing operation requires the use of diffusers in the reference beam path to provide a unique code for each object wave. In this thesis, various types of diffusers are analyzed and compared within the framework of multiplex holography. A simple model is initially developed which can accommodate a wide range of diffuser families, including pure phase, pure amplitude, and combined amplitude and phase diffusers. Crosscorrelation and autocorrelation calculations are then presented for both spherical wave (chirp) illumination and plane wave illumination, and a signal-to-noise analysis based on these calculations is included. Finally, the implications of the analysis are thoroughly discussed, and recommendations for further research are given.Item Fabrication of binary phase diffusers for space-variant processing(Texas Tech University, 1983-12) Chase, Scott BTechniques have previously been described for holographically representing space-variant systems. By spatially sampling the input plane and using phase mask diffusers to encode the multiple reference beams, one can sequentially record holograms exhibiting a minimal amount of crosstalk. Gold-coded binary phase masks have been shown to have good correlation properties with known cross-correlation bounds. This thesis describes a technique which generates phase masks using a laser scanner computer generated hologram (CGH) writing f a c i l i t y at a wavelength of 4579A. Methods for determining the proper resist thickness to achieve the necessary 180 degree phase shift between adjacent cells in a mask include analyzing the data taken by an interference microscope and quantitative analysis of the dc component present in the Fourier spectrum of the mask. Comparisons of the effectiveness of the phase masks with that of ground-glass were obtained using two different tests. First, the phase masks were used in a space-variant processor, and the results of the multiplexed holograms were compared to those obtained earlier using a ground-glass diff user. Secondly, computer-generated holograms were made using the phase masks as diffusers and the results were compared with those previously obtained using amplitude masks.Item Maximizing Crosstalk-Induced Slowdown During Path Delay Test(2012-10-19) Gope, DibakarCapacitive crosstalk between adjacent signal wires in integrated circuits may lead to noise or a speedup or slowdown in signal transitions. These in turn may lead to circuit failure or reduced operating speed. This thesis focuses on generating test patterns to induce crosstalk-induced signal delays, in order to determine whether the circuit can still meet its timing specification. A timing-driven test generator is developed to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. The test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. By using path delay information obtained from circuit preprocessing, preferred paths can be chosen during aggressor path propagation processes. As the test generator sensitizes aggressors in the presence of victim path necessary assignments, the search space is effectively reduced for aggressor path generation. This helps in reducing the test generation time for aligned aggressors. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. The proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths.Item Multiplex holography for space-variant optical processing(Texas Tech University, 1979-08) Jones, Mike IvorThis thesis describes extensive experimental implementations of multiplex holography for use in representing two-dimensional spacevariant optical systems. Diffusers are used to encode the reference beams for effective crosstalk suppression. The problem of hologramto-hologram crosstalk is both analytically and experimentally examined, and various methods for its suppression are discussed. The merits of using ground glass diffusers for crosstalk suppression are experimentally investigated, and the superiority of chirped-wave diffuser illumination over plane-wave illumination in crosstalk suppression is demonstrated. The first implementations of binary-coded diffuser masks for crosstalk suppression in multiplex holography are shown. The experimental proof of coherent addition in overlapping holographic outputs is presented, and the first holographic representation of an extremely space-variant optical system is shown. The holographic representation of an optical system using a large (10 x 10) array of input sampling points is also shown. With a working 2-D space-variant holographic processor thus available, a variety of space-variant processing operations for future investigations are suggested.Item Statistical static timing analysis considering process variations and crosstalk(Texas A&M University, 2005-11-01) Veluswami, SenthilkumarIncreasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have become dominant and it is imperative to model them to obtain accurate timing analysis results. In addition, intra-die process variations are spatially correlated due to pattern dependencies in the manufacturing process. Any statistical static timing analysis (SSTA) tool is incomplete without a model for signal crosstalk, as critical path delays can increase or decrease depending on the switching of capacitively coupled nets. The coupled signal timing in turn depends on the process variations. This work describes an SSTA tool that models signal crosstalk and spatial correlation in intra-die process variations, along with gradients and inter-die variations.Item Track Assignment Considering Crosstalk-Induced Performance Degradation(2012-07-16) Zhao, QiongTrack assignment is a critical step between global routing and detailed routing in modern VLSI chip designs. It greatly affects some very important design characteristics, such as routability, via usage and timing performance. Crosstalk, which is largely decided by wire adjacency, has significant impact on interconnect delay and circuit performance. Therefore, the amount of crosstalk should be restrained in order to satisfy timing constraints. In this work, a track assignment approach is proposed to control crosstalk-induced performance degradation. The problem is formulated as a Traveling Salesman Problem (TSP) and solved by a graph-based heuristic. The proposed approach is implemented and tested on benchmark circuits from the ISPD2011 contest and the experimental results are quite promising.