Browsing by Subject "Contact resistance"
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Item Device physics and device mechanics for flexible MoS2 thin film transistors(2015-08) Chang, Ph. D., Hsiao-Yu; Akinwande, Deji; Lu, Nanshu; Lee, Jack; Lai, Keji; Dodabalapur, AnanthWhile there has been increasing studies of MoS2 and other two-dimensional (2D) semiconducting dichalcogenides on hard conventional substrates, experimental or analytical studies on flexible substrates has been very limited so far, even though these 2D crystals are understood to have greater prospects for flexible smart systems. In the first part, we report detailed studies of MoS2 transistors on industrial plastic sheets. Failure mechanisms under strain are studied with bending test and stretching test. Experimental investigation identifies that crack formation in the dielectric and the buckling delamination in MoS2 are responsible for the degradation of the device performance. Several approaches to improve device flexibility were discussed. In the second part, electronic transport properties in multilayer MoS2 are investigated with Y-function method. By combining experiments and analysis, we show that the Y-function method offers a robust route for evaluating the low-field mobility, threshold voltage and contact resistance even when the contact is a Schottky-barrier as is common in two-dimensional transistors. In addition, an independent transfer length method (TLM) evaluation corroborates the modified Y-function analysis. The last part, we demonstrate the first RF performance for transferred CVD-grown MoS2 FETs on the flexible substrate. Our result suggests that the large-area CVD-grown MoS2 provides a practical route to realize low-power, high speed electronics circuit applications in the future.Item Optimization and yield enhancement for measuring contact resistance in large scale microprocessors(2008-12) Reich, Jonathan R.; Nutter, Brian; Gale, Richard O.As semiconductor technology advances, the functionality and complexity of microprocessors increase. Establishing proper test methods is an important electrical characteristic of testing a DUT (Device Under Test). With a large scale microprocessor’s pin count exceeding one thousand, abstract methods must be used to insure proper test integration between the tester and DUT. Because the majority of tests performed on high-end microprocessors are complex and sensitive to noise, it is becoming more important that quality electrical connections are being made. The purpose of this thesis is to tighten CRes test limits so solder ball integrity can be verified to eliminate a test insertion from the production test flow. Previous CRes limits were relaxed due to complications while testing CRes. These complications and solutions will be addressed in this thesis. This thesis will describe methods of testing and optimization to enhance yield while testing contact resistance (CRes) on large pin count SUN Niagara 2 and Victoria Falls microprocessors using a LTX Fusion VX4/VX5 tester. This thesis will also discuss test methods to reduce mechanical error associated between the tester and the DUT.