Browsing by Subject "Code generators"
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Item A parallel compiler for SequenceL(Texas Tech University, 2002-08) Andersen, Per H.Procedural languages like C and FORTRAN have historically been the languages of choice for implementing programs for high performance parallel computers. This dissertation is an investigation of a high-level nested programming language, SequenceL and whether a SequenceL compiler that compiles to parallel code can be developed for a parallel system. This dissertation has achieved the following results. • Established a proof of concept that there exists a SequenceL compiler that can create executable programs that embody the inherent parallelisms and other implied controls structures in SequenceL, • Developed a new intermediate language capable of representing the meaning of a SequenceL source program, • Developed the techniques for spawning threads to dynamically create parallelisms using a threaded approach, and discovered that the SequenceL language implies a parallel execution model, • Identified a number of optimization and performance enhancement opportunities, • Identified a new SequenceL language requirement for defining nesting and cardinality typing information for SequenceL data structures.Item Adaptive predication via compiler-microarchitecture cooperation(2007) Kim, Hyesoon, 1974-; Patt, Yale N.Even after decades of research in branch prediction, branch predictors still remain imperfect, which results in significant performance loss in aggressive processors that sup- port large instruction windows and deep pipelines. Predicated execution can reduce the number of branch mispredictions by eliminating hard-to-predict branches. However, the additional instruction overhead and data dependencies due to predicated execution some- times offset the performance benefits of having fewer mispredictions. This dissertation presents two cooperative compiler-microarchitecture mechanisms to reduce the branch mis- prediction penalty by combining predicated execution and branch prediction. The first mechanism is a set of new control flow instructions, called wish branches. With wish branches, the compiler generates code that can be executed either as normal branch code or as predicated code. At run-time, the hardware chooses between normal branch code and predicated code based on the run-time branch behavior and the estimated run-time effectiveness of each solution. The results show that wish branches can signifi- cantly improve both performance and energy efficiency compared to predication or branch prediction. To provide the benefit of predicated code to non-predicated Instruction Set Archi- tectures (ISAs) and to increase the benefit of predicated execution beyond the benefit of wish branches, this dissertation also presents and evaluates the Diverge-Merge Processor (DMP) architecture. In the diverge-merge processor, the compiler analyzes the control-flow graphs of the program and marks branches suitable for dynamic predication –called di- verge branches– and their corresponding control flow merge points. The hardware not only chooses whether to use branch prediction or predication, but also decides “which” instruc- tions after a branch should be predicated based on run-time branch behavior. This solution significantly reduces the overhead of predicated code and allows a very large set of control- flow graphs to be predicated, neither of which was possible previously because predication was performed statically without any run-time information. This dissertation compares DMP with all other major previously-proposed branch processing paradigms available in the literature in terms of performance, power, energy consumption, and complexity. The results show that DMP is the most energy-efficient and high-performance paradigm for branch handling. Code generation algorithms for the DMP architecture and cost-benefit analysis models of dynamic predication are also evaluated.Item