Browsing by Subject "CMOS"
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Item A 200-MHz fully-differential CMOS front-end with an on-chip inductor for magnetic resonance imaging(Texas A&M University, 2007-04-25) Ayala, Julio Enqrique, IIRecently, there is a growing interest in applying electronic circuit design for biomedical applications, especially in the area of nuclear magnetic resonance (NMR). NMR has been used for many years as a spectroscopy technique for analytical chem- istry. Previous studies have demonstrated the design and fabrication of planar spiral inductors (microcoils) that serve as detectors for nuclear magnetic resonance mi- crospectroscopy. The goal of this research was to analyze, design, and test a prototype integrated sensor, which consisted of a similar microcoil detector with analog components to form a multiple-channel front-end for a magnetic resonance imaging (MRI) system to perform microspectroscopy. The research has succeeded in producing good function- ality for a multiple-channel sensor. The sensor met expectations compared to similar one-channel systems through experiments in channel separation and good signal-to- noise ratios.Item A 3.125 Gb/s 5-TAP CMOS Transversal Equalizer(2010-07-14) Lopez-Rivera, Marcos L.Recently, there is growing interest in high speed circuits for broadband communication, especially in wired networks. As the data rate increases beyond 1 GB/s conventional materials used as communication channels such as PCB traces, coaxial cables, and unshielded twisted pair (UTP) cables, etc. attenuate and distort the transmitted signal causing bit errors in the receiver end. Bit errors make the communication less reliable and in many cases even impossible. The goal of this work was to analyze, and design an channel equalizer capable of restoring the received signal back to the original transmitted signal. The equalizer was designed in a standard CMOS 0.18 ?m process and it is capable of compensating up to 20 dB?s of attenuation at 1.5625 GHz for 15 and 20 meters of RG-58 A/U coaxial cables. The equalizer is able to remove 0.5 UI ( 160 ps ) of peak-to-peak jitter and output a signal with 0.1 UI ( 32 ps ) for 15 meters of cable at 3.125 Gb/s. The equalizer draws 18 mA from a 1.8 V power supply which is lower than publications [1, 2] for CMOS transversal equalizers.Item Atomic-scale modeling and experimental studies for dopants and defects in Si and SiGe nano-scale CMOS devices(2010-05) Kim, Yonghyun; Banerjee, Sanjay; Kirichenko, Taras A.; Lee, Jack Chung-Yeung; Register, Leonard F.; Tutuc, Emanuel; Henkelman, GraemeContinued scaling of CMOS devices with Si and SixGe1-x down to 22 nm design node or beyond will require the formation of ever shallower and more abrupt junctions with higher doping levels in order to manage the short channel effects. With the increasing importance of surface proximity and stress effects, the lateral diffusion in gate-extension overlap region strongly influences both threshold voltage roll-off degradation and DIBL increase by requiring an optimized abruptness and diffusion for better device performance. Therefore, the detailed understanding of defect-dopant interactions in the disordered and/or strained systems is essential to develop a predictive kinetic model for the evolution of dopant concentration and electrical activation profiles. Our density functional theory calculations provide the guidance for experimental designs to realize ultra-shallow junction formation required for future generations of nano-scale CMOS devices. Few systematic studies in epitaxially-grown SixGe1-x channel CMOS have been reported. The physical mechanisms of boron diffusion in strained SixGe1-x/Si heterojunction layers with different SixGe1-x layer thicknesses and Ge content (>50%) are addressed, especially with high temperature annealing. In addition, the effects of the fluorine incorporated during BF2 implant on boron diffusion are investigated to provide more insight into short channel device design. In this study, we investigate how short channel margins are affected by Ge mole fraction and SixGe1-x layer thickness in a compressively strained SixGe1-x/Si heterojunction PMOS with high temperature annealing. Series resistance characterization in S/D extension region and gate oxide interface trap characterization for Si, SixGe1-x, and Ge nMOSFETs are done. TCAD device simulation is also performed to evaluate which distributions of interface traps will significantly affect the electrical characteristics such as flatband voltage (VFB) shift and threshold voltage (Vth) shift based on capacitance-voltage (CV) and current-voltage (IV) curves. n+/p and p+/n diode structures are studied in order to decouple the electrical characteristics from the gated-diode (GD) MOSFETs. With the extraction of S/D series resistance from various channel lengths, possible reasons for performance degradation in SixGe1-x and Ge nMOSFETs, based on simulations, are proposed.Item Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques(2012-02-14) Kim, Ju SungFuture wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.Item Built-in self test of RF subsystems(2008-12) Zhang, Chaoming, 1980-; Abraham, Jacob A.With the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Item Circuit techniques for programmable broadband radio receivers(2013-12) Forbes, Travis Michael, 1986-; Gharpurey, RanjitThe functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF.Item A comprehensive study of 3D nano structures characteristics and novel devices(2008-12) Zaman, Rownak Jyoti; Banerjee, SanjaySilicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques.Item Design and implementation of low power multistage amplifiers and high frequency distributed amplifiers(Texas A&M University, 2005-11-01) Mishra, ChinmayaThe advancement in integrated circuit (IC) technology has resulted in scaling down of device sizes and supply voltages without proportionally scaling down the threshold voltage of the MOS transistor. This, coupled with the increasing demand for low power, portable, battery-operated electronic devices, like mobile phones, and laptops provides the impetus for further research towards achieving higher integration on chip and low power consumption. High gain, wide bandwidth amplifiers driving large capacitive loads serve as error amplifiers in low-voltage low drop out regulators in portable devices. This demands low power, low area, and frequency-compensated multistage amplifiers capable of driving large capacitive loads. The first part of the research proposes two power and area efficient frequency compensation schemes: Single Miller Capacitor Compensation (SMC) and Single Miller Capacitor Feedforward Compensation (SMFFC), for multistage amplifiers driving large capacitive loads. The designs have been implemented in a 0.5??m CMOS process. Experimental results show that the SMC and SMFFC amplifiers achieve gain-bandwidth products of 4.6MHz and 9MHz, respectively, when driving a load of 25Kδ/120pF. Each amplifier operates from a ??1V supply, dissipates less than 0.42mW of power and occupies less than 0.02mm2 of silicon area. The inception of the latest IEEE standard like IEEE 802.16 wireless metropolitan area network (WMAN) for 10 -66 GHz range demands wide band amplifiers operating at high frequencies to serve as front-end circuits (e.g. low noise amplifier) in such receiver architectures. Devices used in cascade (multistage amplifiers) can be used to increase the gain but it is achieved at an expense of bandwidth. Distributing the capacitance associated with the input and the output of the device over a ladder structure (which is periodic), rather than considering it to be lumped can achieve an extension of bandwidth without sacrificing gain. This concept which is also known as distributed amplification has been explored in the second part of the research. This work proposes certain guidelines for the design of distributed low noise amplifiers operating at very high frequencies. Noise analysis of the distributed amplifier with real transmission lines is introduced. The analysis for gain and noise figure is verified with simulation results from a 5-stage distributed amplifier implemented in a 0.18??m CMOS process.Item Design of a 3.1-4.8 GHZ RF front-end for an ultra wideband receiver(Texas A&M University, 2006-08-16) Sharma, PushkarIEEE 802.15 High Rate Alternative PHY task group (TG3a) is working to define a protocol for Wireless Personal Area Networks (WPANs) which makes it possible to attain data rates of greater than 110Mbps. Ultra Wideband (UWB) technology utilizing frequency band of 3.168 GHz ? 10.6 GHz is an emerging solution to this with data rates of 110, 200 and 480 Mbps. Initially, UWB mode I devices using only 3.168 GHz ? 4.752 GHz have been proposed. Low Noise Amplifier (LNA) and I-Q mixers are key components constituting the RF front-end. Performance of these blocks is very critical to the overall performance of the receiver. In general, main considerations for the LNA are low noise, 50 broadband input matching, high gain with maximum flatness and good linearity. For the mixers, it is essential to attain low flicker noise performance coupled with good conversion gain. Proposed LNA architecture is a derivative of inductive source degenerated topology. Broadband matching at the LNA output is achieved using LC band-pass filter. To obtain high gain with maximum flatness, an LC band-pass filter is used at its output. Proposed LNA achieved a gain of 15dB, noise figure of less than 2.6dB and IIP3 of more than -7dBm. Mixer is a modified version of double balanced Gilbert cell topology where both I and Q channel mixers are merged together. Frequency response of each sub-band is matched by using an additional inductor, which further improves the noise figure and conversion gain. Current bleeding scheme is used to further reduce the low frequency noise. Mixer achieves average conversion gain of 14.5dB, IIP3 more than 6dBm and Double Side Band (DSB) noise figure less than 9dB. Maximum variation in conversion gain is desired to be less than 1dB. Both LNA and mixers are designed to be fabricated in TSMC 0.18??m CMOS technology.Item Design of large time constant switched-capacitor filters for biomedical applications(Texas A&M University, 2005-02-17) Tumati, SanjayThis thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.Item Electromagnetic Interference (EMI) Resisting Analog Integrated Circuit Design Tutorial(2012-10-19) Yu, JingjingThis work introduces fundamental knowledge of EMI, and presents three basic features correlated to EMI susceptibility: nonlinear distortion, asymmetric slew rate (SR) and parasitic capacitance. Different existing EMI-resisting techniques are analyzed and compared to each other in terms of EMI-Induced input offset voltage and other important specifications such as current consumption. In this work, EMI-robust analog circuits are proposed, of which the architecture is based on source-buffered differential pair in the previous publications. The EMI performance of the proposed topologies has been verified within a test IC which was fabricated in NCSU 0.5um CMOS technology. Experimental results are presented when an EMI disturbance signal of 400mV and 800mV amplitude was injected at the input terminals, and compared with a conventional and an existing topology. The tested maximal EMI-induced input offset voltage corresponds to -222mV for the new structure, which is compared to -712mV for the conventional one and -368mV for the one using existing source-buffered technique in literature. Furthermore the overall performances of the circuits such as current consumption or input referred noise are also provided with the corresponding simulation results.Item Fully integrated cmos phase shifter/vco for mimo/ism application(2009-05-15) Tavakoli Hosseinabadi, Ahmad RezaA fully integrated CMOS 0 ? 900 phase shifter in 0.18um TSMC technology is presented. With the increasing use of wireless systems in GHz range, there is high demand for integrated phase shifters in phased arrays and MIMO on chip systems. Integrated phase shifters have quite a high number of integrated inductors which consume a lot of area and introduce a huge amount of loss which make them impractical for on chip applications. Also tuning the phase shift is another concern which seems difficult with use of passive elements for integrated applications. This work is presents a new method for implementing phase shifters using only active CMOS elements which dramatically reduce the occupied area and make the tuning feasible. Also a fully integrated millimeter-wave VCO is implemented using the same technology. This VCO can be part of a 24 GHz frequency synthesizer for 24 GHz ISM band transceivers. The 24 GHz ISM band is the unlicensed band and available for commercial communication and automotive radar use, which is becoming attractive for high bandwidth data rate.Item Germanium and epitaxial Ge:C devices for CMOS extension and beyond(2011-08) Jamil, Mustafa; Banerjee, Sanjay; Colombo, Luigi; Register, Leonard F.; Tutuc, Emanuel; Tsoi, MaximThis work focuses on device design and process integration of high-performance Ge-based devices for CMOS applications and beyond. Here we addressed several key challenges towards Ge-based devices, such as, poor passivation, underperformance of nMOSFETs, and incompatibility of fragile Ge wafers for mass production. We simultaneously addressed the issues of bulk Ge and passivation for pMOSFETs, by fabricating Si-capped epitaxial Ge:C(C<0.5%) devices. Carbon improves the crystalline quality of the channel, while Si capping prevents GeOx formation, creates a quantum well for holes and thus improves mobility. Temperature-dependent characterization of these devices suggests that Si cap thickness needs to be optimized to ensure highest mobility. We developed a simple approach to grow GeO₂ by rapid thermal oxidation, which provides improved passivation, especially for nMOSFETs. The MOSCAPs with GeO₂ passivation show ~10× lower Dit (~8×10¹¹ cm⁻²eV⁻¹) than that of the HF-last devices. The Ge (111) nMOSFETs with GeO₂ passivation show ~2× enhancement in mobility (~715 cm²V⁻¹s⁻¹ at peak) and ~1.6× enhancement in drive current over control Si (100) devices. For improved n⁺/p junctions, we proposed a simple technique of rapid thermal diffusion from "spin-on-dopants" to avoid implantation damage during junction formation. These junctions show a high ION/IOFF ratio (~10⁵⁻⁶) and an ideality factor of ~1.03, indicating a low defect density, whereas, ion-implanted junctions show higher Ioff (by ~1-2 orders) and a larger ideality factor (~1.45). Diffusion-doped and GeO₂-passivated Ge(100) nMOSFETs show a high ION/IOFF ratio (~10⁴⁻⁵) , a low SS (111 mV/decade), and a high [mu]eff (679 cm²V⁻¹s⁻¹ at peak). Moreover, diffusion-doped Ge (111) nMOSFETs show even higher [mu]eff (970 cm²V⁻¹s⁻¹ at peak) that surpasses the universal Si mobility at low Eeff. For Beyond CMOS devices, we investigated Mn-doped Ge:C-on-Si (100), a novel Si-compatible ferromagnetic semiconductor. The investigation suggests that the magnetic properties of these films depend strongly on crystalline structure and Mn concentration. On a different approach, we developed LaOx/SiOx barrier for Spin-diodes that reduces contact resistance by ~10⁴, compared to Al₂O₃ controls and hence is more conducive for spin injection. These ferromagnetic materials and devices can potentially be useful for novel spintronic devices.Item High dynamic range CMOS-integrated biosensors(2013-05) Singh, Ritu Raj; Hassibi, ArjangBiosensors are extremely powerful analytical tools instrumental for detection and quantification of bio-molecules such as DNA, peptides and even metabolites. The recent decade has seen a surge in biosensing applications ranging from molecular diagnostics, environmental monitoring, basic life science research, forensics and biothreat monitoring. The existing biosensor systems of today, however, have several limitations. They are expensive, bulky in size, power hungry, hard to use and with access limited to core facilities. Among other disadvantages, these impediments discourage the availability of point-of-care testing and low cost in-vitro diagnostics (IVD) in locations such as developing and third world countries. The main bottleneck in the development of low-cost and compact biosensors is the effective and efficient integration of several complex components present inside a typical biosensor. These components are the sample preparation, biomolecular recognition, signal transduction and data analysis. With vii the recent advancements in very large scale integration (VLSI) and fabrication technologies, it is now possible to integrate several of these biosensing components into a small form factor. This thesis proposes leveraging the utilization of VLSI technology to develop a low-cost, miniature, portable, fast analysis, high throughput and low power consumption biosensor solution. Apart from the miniaturization bene- fits, employing VLSI technology facilitates low-cost, high yield and low process variation. We present complementary metal-oxide semiconductor (CMOS) integrated microsystem solutions for fluorescence, bioluminescence and electrochemical biosensing. Simulation models are provided for the microsystems and the specifications for the constituent components derived. A common problem in the transducer development of biosensors that we specifically focus on, is the presence of a large non-informative signal called the background signal. This background signal can be several orders of magnitudes higher than the signal of interest and it reduces the overall sensitivity of the biosensor. Existing transducer solutions rely on very high dynamic range, expensive and power hungry solutions to solve the problem of high background signal. To address the problem of overwhelming background signal, this thesis proposes an active background subtraction architecture merged with a Σ∆ modulator. The robust, versatile architecture can be conveniently employed for optical and electrochemical sensing. The proposed architecture attenuates the background signal very early in the signal chain, achieving high dyviii namic range while significantly relaxing the performance requirements of the subsequent circuit blocks in terms of power dissipation, area and bandwidth requirements. To validate the proposed solution, two CMOS IC prototypes were developed for optical and electrochemical sensing respectively. A 12 × 12 array of Σ∆ photodetector with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. The pixel performance has been validated with over 140dB dynamic range and the ability of subtract the background subtraction current validated from 10nA to 10fA. Real time pyrosequencing experiment has also been performed utilizing the photodetector array. A 12 × 12 array of Σ∆ electrochemical sensor with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. Capacitive charge redistribution circuit architecture for bipolar current measurements was employed. The circuit performance was validated over the wide input current range of 100nA to 1pA.Item Impedance Spectroscopy Systems Suitable for Biomedical Cell Impedance Measurement(2013-06-03) Huang, HaoImpedance spectroscopy (IS) is an important technique for monitoring and detection of biomaterials. In order to enable point-of-care systems, low-cost IS systems capable of rapidly measuring a wide range of biomaterials are required. This thesis presents two IS systems, one in Printed Circuit Board level and the other in Integrated Circuit level. The board level system is built for preliminary experimental data collection; it is capable of measuring impedance from 1KHz to 100KHz with 200mV signal injection into cell sample. Experimental results show that magnitude and phase error are less than 6.6% and 2.2%, respectively. An IC level IS front-end is also proposed which utilizes a time-to-digital converter (TDC) and a peak detector circuit (PDC) for quick measurement of both impedance phase and magnitude, respectively. Designed in a 0.18?m CMOS process, the front-end is capable of performing impedance measurements in 6?s at frequencies ranging from 100Hz-10MHz and with a 100?-1M? dynamic range. Simulation results with cell impedance models show that the system achieves <2.5% magnitude and <2.2 degree phase error. The front-end consumes 28mW total power and occupies 0.4mm^2 area.Item Integrated impedance spectroscopy biosensors(2012-05) Manickam, Arun; Hassibi, Arjang; Neikirk, Dean P.; Pan, David Z.; Kavusi, SamAffinity-based biosensors, or in short biosensors, are extremely powerful and versatile analytical tools which are used for the detection of a wide variety of bio-molecules. In recent times, there has been a need for developing low-cost and portable affinity-based biosensor platforms. Such systems need to have a high density of detection sites (i.e biosensing elements) in order to simultaneously detect multiple analytes in a single sample. This has led to the creation of integrated biosensors, which make use of integrated circuits (ICs) for bio-molecular detection. In such systems, it has been demonstrated that by taking advantage of the capabilities of semiconductor and very large scale integrated (VLSI) circuit fabrication processes, it is possible to build compact miniaturized biosensors, which can be used in wide variety of applications such as in molecular diagnostics and for environmental monitoring. Among the various detection modalities for biosensors, Electrochemical Impedance Spectroscopy (EIS) permits real-time detection and has label-free detection capabilities. EIS is fully electronic in nature. Hence, it can be implemented using standard IC technologies. The versatility and ease of integration of EIS makes it a promising candidate for developing integrated biosensor platforms. In this thesis, we first examine the underlying principles of EIS method of biosensing. By analyzing an immunosensor assay as an example, we show that EIS based biosensing is a highly sensitive detection method, which can be used for the detection of a wide variety of analytes. Since EIS relies on small impedance changes in order to perform detection, it requires highly accurate models for the electrode-electrolyte systems. Hence, we also introduce a compact modeling technique for the distributed electrode-electrolyte systems with non-uniform electric fields, which is capable of modelling noise and other non-idealities in EIS. In the second part of this thesis, we describe the design and implementation of an integrated EIS biosensor array, built using a standard complementary metal-oxide-semiconductor (CMOS) process. The chip is capable of measuring admittance values as small as 10nS and has a wide dynamic range (90dB) over a wide range of frequencies (10Hz-50MHz). We also report the results obtained from the DNA and protein detection experiments performed using this chip.Item Integrated temperature sensors in deep sub-micron CMOS technologies(2014-05) Chowdhury, Golam Rasul; Hassibi, ArjangIntegrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.Item Low-Power Wireless Medical Systems and Circuits for Invasive and Non-Invasive Applications(2014-04-23) Gaxiola-Sosa, Jesus EfrainApproximately 75% of the health care yearly budget of public health systems around the world is spent on the treatment of patients with chronic diseases. This, along with advances on the medical and technological fields has given rise to the use of preventive medicine, resulting on a high demand of wireless medical systems (WMS) for patient monitoring and drug safety research. In this dissertation, the main design challenges and solutions for designing a WMS are addressed from system-level, using off-the-shell components, to circuit implementation. Two low-power oriented WMS aiming to monitor blood pressure of small laboratory animals (implantable) and cardiac-activity (12-lead electrocardiogram) of patients with chronic diseases (wearable) are presented. A power consumption vs. lifetime analysis to estimate the monitoring unit lifetime for each application is included. For the invasive/non-invasive WMS, in-vitro test benches are used to verify their functionality showing successful communication up to 2.1 m/35 m with the monitoring unit consuming 0.572 mA/33 mA from a 3 V/4.5 V power supply, allowing a two-year/ 88-hour lifetime in periodic/continuous operation. This results in an improvement of more than 50% compared with the lifetime commercial products. Additionally, this dissertation proposes transistor-level implementations of an ultra-low-noise/low-power biopotential amplifier and the baseband section of a wireless receiver, consisting of a channel selection filter (CSF) and a variable gain amplifier (VGA). The proposed biopotential amplifier is intended for electrocardiogram (ECG)/ electroencephalogram (EEG)/ electromyogram (EMG) monitoring applications and its architecture was designed focused on improving its noise/power efficiency. It was implemented using the ON-SEMI 0.5 ?m standard process with an effective area of 360 ?m2. Experimental results show a pass-band gain of 40.2 dB (240 mHz - 170 Hz), input referred noise of 0.47 Vrms, minimum CMRR of 84.3 dBm, NEF of 1.88 and a power dissipation of 3.5 ?W. The CSF was implemented using an active-RC 4th order inverse-chebyshev topology. The VGA provides 30 gain steps and includes a DC-cancellation loop to avoid saturation on the sub-sequent analog-to-digital converter block. Measurement results show a power consumption of 18.75 mW, IIP3 of 27.1 dBm, channel rejection better than 50 dB, gain variation of 0-60dB, cut-off frequency tuning of 1.1-2.29 MHz and noise figure of 33.25 dB. The circuit was implemented in the standard IBM 0.18 ?m CMOS process with a total area of 1.45 x 1.4 mm^(2). The presented WMS can integrate the proposed biopotential amplifier and baseband section with small modifications depending on the target signal while using the low-power-oriented algorithm to obtain further power optimization.Item A low-voltage, low-power CMOS bandgap reference(2010-05) Murugeshappa, Ravi Gourapura; Viswanathan, T. R., doctor of electrical engineering; Hassibi, ArjangBandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage reference for the entire IC. The most used CMOS implementation for voltage references is the bandgap circuit due to its high predictability, and low dependence of the supply voltage and temperature of operation. This work studies a CMOS implementation of a resistor-less bandgap reference, which consumes low power. The most relevant and traditional approaches usually employed to implement bandgap voltage references are investigated. The impact of process, power-supply, load and temperature variations has been analyzed and simulated. The functionality of critical components of the circuit has been verified through chip implementation.Item Memristor based arithmetic circuit design(2016-12) Revanna, Nagaraja; Swartzlander, Earl E., Jr., 1945-; Valvano, Jonathan; Akinwande, Deji; Gerstlauer, Andreas; Schulte, MichaelThe revolution in electronics enabled by Moore’s Law has been driven historically by the ability to fabricate ever smaller features lithographically on planar semiconductor platforms. In recent years, this has been slowing down due to the myriad of problems in short channel CMOS technologies. Research is now focusing on realizing Moore’s law by architectural innovation, involving novel circuits and computation paradigms. There has been intense interest and activity directed towards designing logic circuits with memory elements. This is mainly driven by ideas like in-memory compute where logic operations are performed at the memory location in order to overcome the memory-wall bottleneck. Resistive-switching random-access memory (RRAM)/ memristors has a great potential to be the future of non-volatile memory owing to its CMOS compatibility, read-write endurance, power and speed. We describe novel high speed logic circuits for adders and multipliers built with RRAM to support the concept of logic-in-memory. These circuits have significant speed/area/power improvements over the existing designs. The complexity involved in computation in terms of controlling the basic gates, sequence of operations etc. has been significantly reduced. RRAM properties are exploited with the help of a well-known analog element called current mirror. Previously known logic-implication technique to realize digital gates comes with a serious limitation of limited fan-out. By using current mirrors, this limitation can be overcome, enabling more logic operations to run in parallel. Results show that the delay for even an XOR operation can be reduced to 1 cycle, compared to the 5 cycles taken by logic implication. Spice simulations are done with known RRAM models. Simulation results show significant improvement in power consumed over the existing designs. The design of different adders and multipliers are also described. Metrics like area, power and latency are compared, and it shows significant improvement over the state-of-the-art.