Browsing by Subject "Built in self test (BIST)"
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Item AC measurements using a built in self test(2006-12) Nesty, Arthur N.; Parten, Michael E.; Nutter, Brian; Cox, Ronald H.Microprocessors are designed in order to interface with other processors or components at speeds that are constantly increasing. This speed increase is a desired effect in the semiconductor industry, as it opens the world to more computing power within compact technologies, including cell phones, gaming systems and super computers. The implementation of these technologies is desired by consumers, as they give quick access to information. However, this poses specific problems to suppliers of these Integrated Circuits. In order for these microprocessors to be of any use to the consumers, they must fall within the bounds of desired specifications that will best describe their behavior. The ability to guarantee these specifications for every device before being introduced into the market becomes difficult and expensive at the speeds desired at present and in the future.Item MARKOV source based test length optimized scan built-in-self-test architecture(Texas Tech University, 2008-08) Farooqi, Aftab A.This dissertation presents several algorithmic and hardware design improvements to some of the recently proposed works using Markov sources for the scan built-in-test architecture. The first improvement is the use of the total probability rule and on-chip quantized probabilities to compute the sampling probability of the deterministic test cubes. Test cubes with low sampling probability are excluded from the final test set used to compute the transition probabilities. The second improvement is the use of new technique called dynamic transition selection, which combines transition inversion and transition fixing to produce test sequences. The third improvement is a new hardware design of the Markov source. Automatic Test Pattern Generator (ATPG) and fault simulator (HOPE) academic tools are used for generating deterministic test cubes and fault simulation, respectively. Espresso is used for logic minimization. The Sequential circiuit Synthesis tool (SIS) is used to map the synthesized design into a generic nand-nor library. Gate Equivalent (GE) count method [18] that reflects a static Complementary Metal Oxide Semiconductor (CMOS) technology: 0.5 GE for an inverter or a transmission multiplexer, (0.5)(n) GE’s for an n-input nand or nor, and (2.5)(n-1) GE’s for an n-input eXclusive-or (XOR) is used. The 5 larger International Symposium on Circuits and Systems (ISCAS89) benchmark circuits are tested using the new test pattern generator. The new test pattern generator achieves complete coverage of the stuck-at faults at signficantly reduced test length, with a modest increase in the gate count.