Browsing by Subject "Atomic layer deposition"
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Item Atomic layer deposition of amorphous hafnium-based thin films with enhance thermal stabilities(2010-12) Wang, Tuo, 1983-; Ekerdt, John G.; Demkov, Alexander A.; Hwang, Gyeong S.; Korgel, Brian A.; Mullins, C. B.The continuous scaling of microelectronic devices requires high permittivity (high-k) dielectrics to replace SiO₂ as the gate material. HfO₂ is one of the most promising candidates but the crystallization temperature of amorphous HfO₂ is too low to withstand the fabrication process. To enhance the film thermal stability, HfO₂ is deposited using atomic layer deposition (ALD), and incorporated with various amorphizers, such as La₂O₃, Al₂O₃, and Ta₂O₅. The incorporation is achieved by growing multiple ALD layers of HfO₂ and one ALD layer of MO[subscript x] (M = La, Al, and Ta) alternately (denoted as [xHf + 1M]), and the incorporation concentration can be effectively controlled by the HfO₂-to-MO[subscript x] ALD cycle ratio (the x value). The crystallization temperature of 10 nm HfO₂ increases from 500 °C to 900 °C for 10 nm [xHf + 1M] film, where x = 3, 3, and 1 for M = La, Al, and Ta, respectively. The incorporation of La₂O₃, and Ta₂O₅ will not compromise the dielectric constant of the film because of the high-k nature of La₂O₃, and Ta₂O₅. Angle resolved X-ray photoelectron spectroscopy (AR-XPS) reveals that when the HfO₂-to-MO[scubscript x] ALD cycle ratio is large enough (x > 3 and 4 for La and Al, respectively), periodic structures exist in films grown by this method, which are comprised of repeated M-free HfO₂ ultrathin layers sandwiched between HfM[subscript x]O[scubscript y] layers. Generally, the film thermal stability increases with thinner overall thickness, higher incorporation concentration, and stronger amorphizing capability of the incorporated elements. When the x value is low, the films are more like homogeneous films, with thermal stabilities determined by the film thickness and the amorphizer. When the x value is large enough, the periodically-repeated structure may add an extra factor to stabilize the amorphous phase. For the same incorporation concentration, films with an appropriately high periodicity may have an increased thermal stability. The manner by which the periodic structure and incorporated element affect thermal stability is explored and resolved using nanolaminates comprised of alternating layers of [scubscript y]HfO₂ and [xHf + 1M] × n, where y varied from 2 to 20, x varied from 1 to 2, and n varied from 4 to 22.Item Atomic layer deposition of functional materials(2015-05) Ngo, Thong Quang; Ekerdt, John G.; Demkov, Alexander A.; Hwang, Gyeong S.; Ellison, Christopher J.; Korgel, Brian A.Atomic layer deposition (ALD) has emerged as an important technique for depositing thin films in both scientific research and industrial applications. The goal of this work is to integrate functional materials using ALD including high-κ dielectric, LaAlO₃, ferroelectric BaTiO₃, photocatalytic CoO, and room temperature ferromagnetic thin films of Co metal for spin-transfer torque random-access memory applications. The work is also to demonstrate the formation of a quasi-two-dimensional electron gas (2-DEG) at the γ-Al₂O₃/SrTiO₃ heterointerface enabling a method for all-oxide device manufacturing using ALD. High permittivity oxide thin films are needed to replace SiO₂ in complementary metal oxide semiconductor (CMOS) transistors. The replacement of SiO₂ by hafnium oxide-based high-κ materials in CMOS devices in 2007 was a revolutionary development in semiconductor front end of line. The continued device feature shrinking requires higher-κ dielectrics, compared to HfO₂-based materials. Crystalline perovskite oxides, such as SrTiO₃, LaAlO₃, and BaTiO₃, etc. have from high to very high dielectric constant and being proposed to replace HfO₂-based materials in CMOS devices if the leakage problem is resolved. The work explores the monolithic integration of crystalline perovskite oxide films with Si(001) using combined molecular beam epitaxy (MBE) and ALD techniques. Four unit cells of SrTiO₃ were grown directly on Si(001) by MBE and transferred in-situ into the ALD chamber for further depositions. The integration of oxide thin films on Si(001) using the MBE-ALD technique allows us to maintain clean oxide/Si(001) interfaces since low temperatures (180–250 °C) were maintained during the ALD deposition. The goal of my work is also to explore processes to enable area selective deposition of cobalt (II) oxide, CoO. The effectiveness of poly(trimethylsilylstyrene) in selectively inhibiting surface nucleation of CoO on SiO₂ and MgO substrates is demonstrated. Carbon-free cobalt thin films are formed by reducing CoO using Al and Sr metals to scavenge oxygen from CoO. The work explores the ability to control the structure and morphology of the resultant cobalt film by tuning the reduction conditions, allowing us to tune magnetic properties of the cobalt thin film. My work also focuses on the growth of γ-Al₂O₃ on the TiO₂-terminated SrTiO₃ substrate at temperatures higher than 300 °C. The formation of a quasi-2-DEG is found at the γ-Al₂O₃/TiO₂-terminated SrTiO₃ interface. In-situ x-ray photoelectron spectroscopy reveals the presence of Ti³⁺ feature at the heterointerface. Conductivity at the interface was found to be proportional to the amount of Ti³⁺ species. Oxide quasi-2-DEG might provide opportunities for new generations of all-oxide electronic devices using ALD.Item Electron transport in graphene transistors and heterostructures : towards graphene-based nanoelectronics(2012-05) Kim, Seyoung, 1981-; Banerjee, Sanjay; Tutuc, Emanuel, 1974-; MacDonald, Allan; Dodabalapur, Ananth; Lee, Jack C.; Register, Leonard F.Two graphene layers placed in close proximity offer a unique system to investigate interacting electron physics as well as to test novel electronic device concepts. In this system, the interlayer spacing can be reduced to value much smaller than that achievable in semiconductor heterostructures, and the zero energy band-gap allows the realization of coupled hole-hole, electron-hole, and electron-electron two-dimensional systems in the same sample. Leveraging the fabrication technique and electron transport study in dual-gated graphene field-effect transistors, we realize independently contacted graphene double layers separated by an ultra-thin dielectric. We probe the resistance and density of each layer, and quantitatively explain their dependence on the backgate and interlayer bias. We experimentally measure the Coulomb drag between the two graphene layers for the first time, by flowing current in one layer and measuring the voltage drop in the opposite layer. The drag resistivity gauges the momentum transfer between the two layers, which, in turn, probes the interlayer electron-electron scattering rate. The temperature dependence of the Coulomb drag above temperatures of 50 K reveals that the ground state in each layer is a Fermi liquid. Below 50 K we observe mesoscopic fluctuations of the drag resistivity, as a result of the interplay between coherent intralayer transport and interlayer interaction. In addition, we develop a technique to directly measure the Fermi energy in an electron system as a function of carrier density using double layer structure. We demonstrate this method in the double layer graphene structure and probe the Fermi energy in graphene both at zero and in high magnetic fields. Last, we realize dual-gated bilayer graphene devices, where we investigate quantum Hall effects at zero energy as a function of transverse electric field and perpendicular magnetic field. Here we observe a development of v = 0 quantum Hall state at large electric fields and in high magnetic fields, which is explained by broken spin and valley spin symmetry in the zero energy Landau levels.Item Monolithic integration of crystalline oxides on silicon and germanium using atomic layer deposition(2015-05) McDaniel, Martin Douglas; Ekerdt, J. G. (John G.); Demkov, Alexander A; Yu, Edward T; Mullins, Charles B; Manthiram, ArumugamInside your microelectronic devices there are up to a billion transistors working in flawless operation. Silicon has been the workhorse semiconductor used for the transistor; however, there must be a transition to materials other than silicon, such as germanium, with future device sizes. In addition, new dielectric oxide materials are needed. My research has examined a type of crystalline oxide, known as a perovskite, which is selected for its ability to bond chemically to Si and Ge, and eliminate the electrical defects that affect performance. Many perovskite oxides are lattice-matched to the Si (001) and Ge (001) surface spacing, enabling heteroepitaxy. To date, the majority of research on crystalline oxides integrated with semiconductors has been based on strontium titanate, SrTiO3, epitaxially grown on Si (001) by molecular beam epitaxy. Alternative low-temperature growth methods, such as atomic layer deposition (ALD), offer both practical and economic benefits for the integration of crystalline oxides on semiconductors. My initial research informed the broader community that four unit cells (~1.5 nm) of SrTiO3 are required to enable heteroepitaxy on Si. The research has also shown that heteroepitaxial layers can be monolithically integrated with Si (001) without the formation of a SiOx interlayer between the Si (001) surface and the SrTiO3 layer because ALD is performed at lower temperatures than are typical for MBE. Thus, a combined MBE-ALD growth technique creates possible advantages in device designs that require the crystalline oxide to be in contact with the Si (001) surface. In recent work, I have demonstrated a method for integrating crystalline oxides directly on Ge by ALD. Germanium is being explored as an alternative channel material due to its higher hole and electron mobilities than Si, potentially enabling device operation at higher speed. This all-chemical growth process is expected to be scalable, is inherently less costly from a manufacturing cost of ownership, and is based on current manufacturing tool infrastructure. The impact of my research will be in continued scaling of device dimensions with novel materials that will provide faster speed and lower power consumption for microelectronic devices.