Browsing by Subject "Asynchronous"
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Item An Asynchronous Network-On-Chip Router with Low Standby Power(2014-11-20) Elshennawy, AmrThe Network-on-Chip (NoC) paradigm is now widely used to interconnect the processing elements (PEs) in a chip multiprocessor (CMP). It has been reported that the NoC consumes about a third of the total power consumption of the multi-core processor. To address this, asynchronous NoC routers have been proposed, to eliminate the clocking power associated with the NoC implementation, which is typically a large fraction of the NoC power consumption. In this work, we present a technique to reduce the standby power of a state-of-the-art asynchronous NoC router. In our approach, the router is put in a known input state when idle, and each gate in the unmodified router is replaced by a logically equivalent gate whose supply pin is connected to a PMOS device with a high threshold voltage in case its output in the idle state was 0. On the other hand, if the output of the unmodified gate in the idle state was 1, it is replaced by a logically equivalent gate whose ground terminal is connected to a NMOS device with a high threshold voltage. Our router is inserted in an NoC, and verified logically for correct routing functionality. We also simulated it at the circuit level using a 45nm fabrication technology, and show that it has a low wake-up time from sleep, and a minimal steady-state routing delay (13%) and area (23%) overhead, and a 8.1? lower standby power, when compared to an unmodified asynchronous NoC router, which was also implemented. Our leakage improvement is achieved in part by using a novel method to control the leakage of the inverter chain used to drive the sleep signal, something which that is not possible with traditional leakage reduction techniques.Item Self-management of external device failures in embedded software systems(2010-12) Mane, Poonam G.; Shin, Michael; Siami-Namin, AkbarThis thesis describes an approach to establishing a framework for detecting failures in the external devices of the embedded systems and self-managing the detected failures. To do this, this thesis develops the detection framework based on the external device types in embedded systems. Each device type is categorized in terms of device characteristics such as input/output, periodic/non-periodic, asynchronous, or active/passive. There are unique communication patterns between the systems and their external devices. These patterns are used to devise failure or fault detection mechanisms. Further, the self-managing framework is developed for handling external device failures from the software perspectives. The self-management is three fold framework - self-healing, self-configuration or adaptation, and self-reporting. The self-healing tries to re-initialize the device and its related attributes to resuscitate the failed devices. The self-configuration adapts the failed device against tolerable failures of devices. The self-reporting reports the intolerable system halting failures to the concerned authorities for further action. The proposed approach in this thesis has been applied to use cases in the elevator system, cruise control system and microwave system.Item A study of SAR ADC and implementation of 10-bit asynchronous design(2013-08) Kardonik, Olga; Sun, NanSuccessive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC’s analog components – comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 µm. Design’s noise and power are presented as a breakdown among components.