Browsing by Subject "Analog-to-digital converters"
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Item A compensation technique for integrator leakage error in sigma-delta modulators(Texas Tech University, 1999-12) Yedevelly, Yeshoda DeviThe common problem faced in many high-resolution Sigma-Delta topologies is their sensitivity to the imperfections of the analog components, especially the integrator. This thesis deals in depth with the physical causes of the deviations in the integrator transfer function 2ind their effects on the Sigma-Delta modulator performance and then proposes a solution for the elimination of the integrator pole error that has been proven as the main error in the integrators. The concept of feedback has been used to eliminate the integrator leakage (pole) error and this concept has been analyzed and also verified by comparing the power spectral densities of two modulators of which, one uses this concept and the other doesn't.Item A high performance class-D amplifier with cascaded sigma-delta modulators(Texas Tech University, 2004-05) Trehan, ChintanThe focus of this thesis is on analysis, simulation and board level implementation of the proposed Class-D power amplifier architecture. The structural design consists of two Sigma-Delta Modulator (SDM) stages in cascade with an intermediate decimation-filter between them. Noise and high tone introduced at the first- stage is filter out through the decimation filter. The signal is converted to a 1-bit Pulse Duration Modulation (PDM) signal by the second stage SDM. The H-Bridge is made part of the SD loop, which enables not only the noise shaping of the quantization noise but also stabilizes the output power switching stage. Output of the H-Bridge is converted to a digital signal using a comparator and latch circuitry and is fed back. To further increase the linearity and performance, high frequency ripples introduced at the H-Bridge is quantized by using a 4-bit SD Analog-to-Digital Converter (ADC) in the feedback loop. Due to the intermediate digital stage and the feedback control at the output stage, the proposed structure has high efficiency and linearity and still is very compact making it possible for wide range of applications.Item A high-resolution charge-redistribution analog-to-digital converter(1985-12) Yung, Henry T.; Chao, Kwong Shu; Gustafson, Donald L.; Anderson, Ronald M.Not AvailableItem A high-speed, high-resolution sigma-delta modulator analog-to-digital converter(Texas Tech University, 2004-05) Fang, LieyiSigma-delta modulators provide the means for achieving high-resolution analog-to- digital conversion. The main limitation faced in the high-resolution Sigma-Delta approach is conversion speed. A multi-stage multi-bit sigma-delta modulator with interstage gain scaling is proposed in this study, and it is designed and implemented in a 0.6 ìm CMOS process. This topology employs a second-order single-bit modulator in the main stage followed by an 8-bit quantizer in pipeline structure. The second stage of the modulator consists of a first-order single-bit modulator followed by a 5-bit quantizer. A gain stage is inserted between the two stages to scale the signal level to within the reference level. System and circuit level simulations have demonstrated that the proposed modulator is capable of achieving high speed and high resolution in analog-to-digital conversion. The detailed design considerations in circuit implementation of the proposed modulator are also analyzed and discussed. The prototype is fabricated in a 0.6 ìm CMOS process with 3.3V power supply. Experimental measurement of the prototype is performed. Several factors limiting the performance are discussed.Item A multibit cascaded sigma-delta modulator with DAC error cancellation techniques(Texas Tech University, 2004-05) Su, Chun-hsienNoise reduction techniques are developed for a multibit cascaded sigma-delta (ÓÄ) modulator used in the analog interface of a digital signal processing system to improve its performance by reducing the errors introduced by digital-to-analog converters (DACs). The idea of the proposed architecture is to create extra feedback paths around the modulator to reduce the DAC errors further by properly designing the error cancellation logic. Transfer functions show that the DAC error at the final stage of the proposed architecture is totally cancelled, while DAC errors from other internal stages are shaped by an order higher than those in a conventional cascaded modulator. The difficulty in circuit implementation of modulators with high resolution and bandwidth increases due to the imperfection of analog components in VLSI processes. Structural and circuit-level compensation techniques are generally used in developing such modulators. Major analog nonideal effects in a multibit cascaded ÓÄ modulator include coefficient mismatches, DAC nonlinearity errors, and integrator leakages. While providing solutions for each of these nonidealities, this dissertation focuses on the minimization of the DAC error since it causes the most performance deterioration. A configurable fourth-order (2-1-1) ÓÄ modulator is implemented for architecture verification. This modulator can be configured as the proposed architecture as well as a conventional cascaded structure with various modulator orders. The design of the system's parameters and analog blocks are fully described in this dissertation. The system is fabricated by the AMI Semiconductor (AMIS) 0.5ìm double-poly triple-metal mixed- signal process through the MOSIS service. Measurement results show that with on-chip error of ±0.15 LSB for each DAC and an oversampling ratio (OSR) of 32, an improvement of 8dB of the proposed architecture over the conventional structure is observed.Item A switched-current CMOS-only parallel pipelined A/D converter(Texas Tech University, 2003-08) Huang, ZhaohuiA pipelined analog-to-digital converter is presented, which employs the switched-current technique to achieve CMOS-only implementation. Four time-interleaved component ADCs are paralleled to increase the throughput to 40Msamples/s, with each operating at the sampling rate of 10MHz. In consideration of linearity and performance, 1.5-bit/stage Digital Error Correction strategy is used and provides 8 effective number of bits for the overall system. For the 0.5pm CMOS implementation, the converter achieves the resolution of 52.1 dB with 500kHz input and its power consumption is 81mW under 3.0V voltage supply. The potential of the ADC is to be integrated in the System-on-Chip for complex applications.Item Analog-to-digital converter circuit and system design to improve with CMOS scaling(2015-05) Mortazavi, Yousof; Evans, Brian L. (Brian Lawrence), 1965-; Hassibi, Arjang; Humphreys, Todd E; Swartlzander, Earl E; Tewfik, Ahmed HThere is a need to rethink the design of analog/mixed-signal circuits to be viable in state-of-the-art nanometer-scale CMOS processes due to the hostile environment they create for analog circuits. Reduced supply voltages and smaller capacitances are beneficial to circuit speed and digital circuit power efficiency; however, these changes along with smaller dimensions and close coupling of fast-switching digital circuits have made high-accuracy voltage domain analog processing increasingly difficult. In this work, techniques to improve analog-to-digital converters (ADC) for nanometer-scale processes are explored. First, I propose a mostly-digital time-based oversampling delta-sigma (∆Σ) ADC architecture. This system uses time, rather than voltage, as the analog variable for its quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital "pulse." The merits of this architecture render it not only viable to scaling, but also enable improved circuit performance with ever-increasing time resolution of scaled CMOS processes. This is in contrast to traditional voltage-based analog circuit design, whose performance generally decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage reduction and short-channel effects. In conjunction with Dr. Woo Young Jung while he was a Ph.D. student at The University of Texas at Austin, two prototype implementations of the proposed architecture were designed and fabricated in TSMC 180 nm CMOS and IBM 45 nm Silicon-On-Insulator (SOI) processes. The prototype ADCs demonstrate that the architecture can achieve bandwidths of 5-20 MHz and ∼50 dB SNR with very small area. The first generation ADC core occupies an area of only 0.0275 mm² , while the second generation ADC core occupies 0.0192 mm² . The two prototypes can be categorized as some of the smallestarea modulators in the literature. Second, I analyze the measured results of the prototype ADC chips, and determine the source for the harmonic distortion. I then demonstrate a digital calibration algorithm that sufficiently mitigates the distortion. This calibration approach falls in the general philosophy of digitally-assisted analog systems. In this philosophy, digital calibration and post-correction are favored over traditional analog solutions, in which there is a high cost to the analog solution either in complexity, power, or area.Item Current-mode analog-to-digital conversion techniques(Texas Tech University, 1993-05) Wong, Kwok ChungThe aim of the research is to develop an A/D converter which is suitable for applications in telecommunication and instrumentation areas and is compatible with the present day CMOS digital process. Viewing the potential advantages offered by current-mode techniques, it is decided to utilize these techniques to realize the converter. In the course of the research, different structures of A/D converters have been developed to enhance the A/D performance.Item Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC(2011-02-22) Gadde, Venkata Veera Satya SairContinuous-time filters are critical components in the implementation of large bandwidth, high frequency, and high resolution continuous-time (CT) sigma-delta (??) analog-to-digital converters (ADCs). The loop filter defines the noise-transfer function (NTF) and hence the quantization noise-shaping behavior of the ?? modulator, and becomes the most critical performance determining part in ?? ADC. This thesis work presents the design considerations for the loop filter in low-pass CT ?? ADC with 12-bits resolution in 25MHz bandwidth and low power consumption using 0.18?m CMOS technology. Continuous-time filters are more suitable than discrete-time filters due to relaxed amplifier bandwidth requirements for high frequency ?? ADCs. A fifth-order low-pass filter with cut-off frequency of 25 MHz was designed to meet the dynamic range requirement of the ADC. An active RC topology was chosen for the implementation of the loop filter, which can provide high dynamic range required by the ?? ADC. The design of a summing amplifier and a novel method for adjusting the group delay in the fast path provided by a secondary feedback DAC of the ?? ADC are presented in detail. The ADC was fabricated using Jazz 0.18?m CMOS technology. The implementation issues of OTAs with high-linearity and low-noise performance suitable for the broadband ADC applications are also analyzed in this work. Important design equations pertaining to the linearity and noise performance of the Gm-C biquad filters are presented. A Gm-C biquad with 100MHz center frequency and quality factor 10 was designed as a prototype to confirm with the theoretical design equations. Transistor level circuit implementation of all the analog modules was completed in a standard 0.18?m CMOS process.Item High speed oversampled analog-to-digital conversion techniques(Texas Tech University, 1993-08) Burra, GangadharNot availableItem High-performance [delta sigma] analog-to-digital conversion(2008-05) Tsang, Robin Matthew, 1979-; Valvano, Jonathan W., 1953-This dissertation is about a new [delta sigma] analog-to-digital converter that offers enhanced quantization noise suppression at low oversampling ratios. This feature makes the converter attractive in applications where speed and resolution are simultaneously demanded. The converter exploits double-sampling for speed, and takes advantage of a new loop-filter to pin down passband quantization noise. A proto-type is fabricated in 0.18-[mu]m CMOS and tested. Results show that at 200-MS/s, the converter achieves an effective number of bits (ENOB) of 12.2-b in a 12.5-MHz signal band while consuming 89-mW from a 1.8-V supply. Using a common performance metric that takes into account of ENOB and signal bandwidth, the prototype outperforms all previously-reported IEEE switched-capacitor [delta sigma] modulators.Item High-resolution analog-to-digital conversion techniques(Texas Tech University, 1988-12) Yung, Henry TNot availableItem Improving flexibility of data acquisition modules(Texas Tech University, 2000-12) Albus, Jonathan ZacharyThe ability for customers to quickly and effectively evaluate general-purpose data converter devices is an important topic that semiconductor manufacturers must address. These systems must be simple enough to quickly and cheaply develop, while still allowing a complete evaluation platform for the target device(s). The integration of dense digital logic into the evaluation module design in the form of CPLD or FPGA technology can provide this ability. This paper documents the design of such an evaluation module, using a CPLD to implement logic control for host-less operation of multiple ADC and DAC devices. Also included is the design of a PC-to-EVM system using Visual Basic 6.0^"^, which allows the customer to evaluate the target ADC(s) using a PC interface and GUI. Each of these techniques developed for a data converter evaluation module can be used to address these same issues for a wide variety of devices.Item Non-binary capacitor array calibration for a high performance successive approximation analog-to-digital converter(2003) Gan, Jianhua; Abraham, Jacob A.; Yan, ShouliIt is very challenging to build precise analog circuits in deep sub-micron and nanometer VLSI fabrication technology. Advanced calibration methods are crucial in designing high performance analog and mixed-signal VLSI circuits. We present a non-binary capacitor array calibration method for a high performance successive approximation analog-to-digital converter (ADC). We show that the capacitor weights are successively refinable under the Markov condition using the rate-distortion theory. Using the analogy to discrete memoryless channel with interference known to the encoder, we show that the interference will not limit the final calibration accuracy if the calibration algorithm adapts to the interference. The capacitor array calibration algorithm is based on a perceptron learning rule, originally developed for Artificial Intelligence applications. It takes advantage of the redundancy in the non-binary capacitor array and the noise in the system to generate the learning cases. We propose a mixed-signal micro-controller architecture to efficiently implement the capacitor array calibration algorithm. A non-binary capacitor array with 20 capacitors is used to design a 16-bit successive approximation ADC. We discuss the design and trade-off of each circuit block in the ADC. We model the thermal noise, flicker noise, power supply interference, charge leakage and harmonic distortion in MATLAB. The calibration is robust under the influence of these nonidealities. The capacitor weights are adaptively calibrated to match the physical capacitors with up to 22-bit accuracy. Capacitor matching is not a limiting factor to the accuracy. The calibration time is about 50 ms. The calibration algorithm can also be used in other mixed-signal circuits to relax the requirement on analog circuits.Item Oversampled multi-bit sigma-delta A/D converters(Texas Tech University, 1997-08) Kinyua, Martin K.The objective of this research is geared towards proposing sigma-delta modulators that will achieve high resolution at wide bandwidths, meaning A/D conversion at rates exceeding 1 MHz with a resolution of at least 12 bits [1, p.219]. As will become clear later, this task not only requires the use of high-order noise shaping but also multi-bit quantization. On that basis, this thesis starts with a basic sigma-delta topology which employs multi-bit quantization with single-bit feedback thus avoiding the very strict linearity requirements imposed on DAC in the feedback path of a sigma-delta loop. The concept is then further extended to develop novel sigma-delta topologies that accomplish a synergetic combination of the advantages of sigma-delta and pipeline ADCs to provide wide dynamic range at wide bandwidths, a performance which may not be currently realized using either of the structures alone. The validity of the proposed topologies is confirmed by system level simulations.Item Pipelined sigma-delta modulators with interstage scaling(Texas Tech University, 1997-12) Chandrasekaran, Ramesh M.Sigma-Delta analog-to-digital converters (lA ADC) are capable of achieving high resolution ( > 15 bits) for moderate signal frequencies (Item Real-time automated data acquisition and control for the Crosbyton Solar Power Project(Texas Tech University, 1980-12) Edwards, William HNot availableItem Sigma-delta modulators with interstage gain scaling(Texas Tech University, 1999-12) Zheng, ZhongqiangThis thesis work describes the efforts made on a new sigma-delta modulator. This unique topology employs an algorithm called interstage gain scaling to depress quantization errors and improve the signal-to-noise ratio (SNR). It consists of two stages: one is a single bit sigma-delta modulator, which is the main stage and the other is a feedback loop stage. At the output of the modulator, the quantization error from the main stage is cancelled while the quantization error from the quantizer in the feedback loop is scaled down by a factor of K. Depending upon the input swing of comparators and operational amplifiers (Opamps) used in the circuits, K can be chosen as 2, 4, 6... For instance, if K is equal to 2, the SNR can be increased by 6 dB or 1 bit compared to the corresponding traditional structure. Successful MATLAB system simulation and PSpice transistor-level simulation in a standard 1.2-um CMOS technology have verified that the proposed sigma-delta modulator is an effective and practicable architecture.Item Study of operational amplifiers' characteristics for driving the inputs of high performance successive approximation register analog-to-digital converters(Texas Tech University, 2003-08) Lewis, Damian PThis study deals with the requirement for driving the inputs of SAR ADCs used in data acquisition systems. The goal of the study is to develop an analysis technique for selecting amplifiers to drive the inputs of single supply, low power SAR ADCs. One of the conditions is that the amplifier selected must be capable of operating on the same power supply as the SAR ADC. The background and work directed towards achieving the above mentioned goal is outlined in the six chapters of this paper. The first chapter gives an overview of data acquisition systems and ADCs in data acquisition systems. The second chapter discusses the operation of CD AC capacitor array for unipolar, bipolar, differential, and single-ended SAR ADCs. The third chapter goes through the requirements of the SAR ADC and an analysis of operational amplifier's parameters and their required values. The fourth chapter shows how to simulate the selected operational amplifier's performance using Pspice. The fifth chapter describes empirical tests characterizing the amplifier's performance. The last chapter is the analysis of the data, conclusion, and recommendation.Item Switched-current analog-to-digital conversion techniques(Texas Tech University, 1995-05) Yilmaz, AbdullahNot available