Browsing by Subject "Analog circuits"
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Item A capacitor-less low drop-out voltage regulator with fast transient response(Texas A&M University, 2006-04-12) Milliken, Robert JonPower management has had an ever increasing role in the present electronic industry. Battery powered and handheld applications require power management techniques to extend the life of the battery and consequently the operation life of the device. Most systems incorporate several voltage regulators which supply various subsystems and provide isolation among such subsystems. Low dropout (LDO) voltage regulators are generally used to supply low voltage, low noise analog circuitry. Each LDO regulator demands a large external capacitor, in the range of a few microfarads, to perform. These external capacitors occupy valuable board space, increase the IC pin count, and prohibit system-on-chip (SoC) solutions. The presented research provides a solution to the present bulky external capacitor LDO voltage regulators with a capacitor-less LDO architecture. The large external capacitor was completely removed and replaced with a reasonable 100pF internal output capacitor, allowing for greater power system integration for SoC applications. A new compensation scheme is presented that provides both a fast transient response and full range ac stability from a 0mA to 50mA load current. A 50mA, 2.8V, capacitor-less LDO voltage regulator was fabricated in a TSMC 0.35um CMOS technology, consuming only 65uA of ground current with a dropout voltage of 200mV. Experimental results show that the proposed capacitor-less LDO voltage regulator exceeds the current published works in both transient response and ac stability. The architecture is also less sensitive to process variation and loading conditions. Thus, the presented capacitor-less LDO voltage regulator is suitable for SoC solutions.Item Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits(2014-12-03) Mukherjee, ParijatVerifying whether a circuit meets its intended specifications, as well as diagnosing the circuits that do not, is indispensable at every stage of integrated circuit design. Otherwise, a significant portion of fabricated circuits could fail or behave correctly only under certain conditions. Shrinking process technologies and increased integration has further complicated this task. This is especially true of mixed-signal circuits, where a slight parametric shift in an analog component can change the output significantly. We are thus rapidly approaching a proverbial wall, where migrating existing circuits to advanced technology nodes and/or designing the next generation circuits may not be possible without suitable verification and debug strategies. Traditional approaches target accuracy and not scalability, limiting their use to high-dimensional systems. Relaxing the accuracy requirement mitigates the computational cost. Simultaneously, quantifying the level of inaccuracy retains the effectiveness of these metrics. We exercise this accuracy vs. turn-around-time trade-off to deal with multiple mixed-signal problems across both the pre- and post-silicon domains. We first obtain approximate failure probability estimates along with their confidence bands using limited simulation budgets. We then generate ?failure regions? that naturally explain the parametric interactions resulting in predicted failures. These two pre-silicon contributions together enable us to estimate and reduce the failure probability, which we demonstrate on a high-dimensional phase-locked loop test-case. We leverage this pre-silicon knowledge towards test-set selection and post-silicon debug to alleviate the limited controllability and observability in the post-silicon domain. We select a set of test-points that maximizes the probability of observing failures. We then use post-silicon measurements at these test-points to identify systematic deviations from pre-silicon belief. This is demonstrated using the phase-locked loop test-case, where we boost the number of failures to observable levels and use the obtained measurements to root-cause underlying parametric shifts. The pre-silicon contributions can also be extended to perform equivalence checking and to help diagnose detected model-mismatches. The resultant calibrated model allows us to apply our work to the system level as well. The equivalence checking and model-mismatch diagnosis is successfully demonstrated using a high-level abstraction model for the phase-locked loop test-case.