Browsing by Subject "Analog Filter"
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Item Design of a 10 MHz Transimpedance Low-Pass Filter with Sharp Roll-Off for a Direct Conversion Wireless Receiver(2010-07-14) Hodgson, James K.A fully-differential base-band transimpedance low-pass filter is designed for use in a direct conversion wireless receiver. Existing base-band transimpedance amplifiers (TIA) often utilize single-pole filters which do not provide good stop-band rejection and may even allow the filter to saturate in the presence of large interferers near the edge of the pass-band. The designed filter is placed in parallel with an existing single-pole TIA filter and diverts stop-band current signals away from the existing filter, providing added rejection and safeguarding the filter from saturating. The presented filter has a bandwidth of 10 MHz, achieves 35 dB rejection at 50 MHz (25 dB in post-layout simulations), and can process interferers as large as 10 mA. The circuit is designed in Jazz 0.18 m CMOS technology, and it is shown, using macromodels, that the design is scalable to smaller, faster technologies.Item Design of a 20MHz Transimpedance Low-pass Filter with an Adapted 3rd Order Inverse Chebyshev Response(2012-10-19) Boakye, EmmanuelIn Multi-Standard receivers, multiple radios co-exist in close proximity. A desired signal can be accompanied by significantly stronger out-of band interferers or blockers, which can severely degrade a receiver's sensitivity through gain compression of the blocks in the receiver chain. This work presents a new Transimpedance Amplifier (TIA) low-pass filter architecture which seeks to solve the out-of-band blocker problem of the existing architectures. A higher order filtering is embedded within the TIA in the form of an active feedback to provide more attenuation to out-of-band blockers. The active feedback circuitry feeds back an equivalent amount of current to the input node to cancel out incoming out-of-band blockers while maintaining an acceptable voltage swing at the output of the TIA. The proposed TIA filter has a channel bandwidth of 20MHz, and can processes interferers of +/- 10mA fully differential without saturating the opamps. The maximum single ended voltage swing at all the nodes is +/- 200mV. All the circuits were designed in IBM 180nm CMOS process with a supply voltage of 1.8V.Item Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications(2013-08-22) Park, Chang JoonSoftware-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal is down-converted to an intermediate frequency and then digitalized. This approach relaxes the specifications for most of the analog front-end building blocks by performing most of the signal processing in the digital domain. However, since the analog-to-digital converter (ADC) is located as close as possible to the antenna in SDR architectures, the ADC specification requirements are very stringent because a large amount of interference signals are present at the ADC input due to the removal of filtering blocks, which particularly affects the dynamic range (DR) specification. Sigma-delta (??) ADCs have several benefits such as low implementation cost, especially when the architecture contains mostly digital circuits. Furthermore, continuous-time (CT) ?? ADCs allow elimination of the anti?aliasing filter because input signals are sampled after the integrator. The bandwidth requirements for the amplifiers in CT ?? ADCs can be relaxed due to the continuous operation without stringing settling time requirements. Therefore, they are suitable for high?speed and low?power applications. In addition, CT ?? ADCs achieve high resolution due to the ?? modulator?s noise shaping property. However, the in-band quantization noise is shaped by the analog loop filter and the distortions of the analog loop filter directly affect the system output. Hence, highly linear low-noise loop filters are required for high-performance ?? modulators. The first task in this research focused on using CMOS 90 nm technology to design and fabricate a 5^(TH)?order active-RC loop filter with a cutoff frequency of 20 MHz for a low pass (LP) CT ?? modulator. The active-RC topology was selected because of the high DR requirement in SDR applications. The amplifiers in the first stage of the loop filter were implemented with linearization techniques employing anti-parallel cancellation and source degeneration in the second stage of the amplifiers. These techniques improve the third-order intermodulation (IM3) by approximately 10 dB; while noise, area, and power consumption do not increase by more than 10%. Second, a current-mode adder-flash ADC was also fabricated as part of a LP CT ?? modulator. The new current-mode operation developed through this research makes possible a 53% power reduction. The new technology also lessens existing problems associated with voltage-mode flash ADCs, which are mainly related to voltage headroom restrictions, speed of operation, offsets, and power efficiency of the latches. The core of the current-mode adder-flash ADC was fabricated in CMOS 90 nm technology with 1.2 V supply; it dissipates 3.34 mW while operating at 1.48 GHz and consumes a die area of 0.0276 mm^(2). System-on chip (SoC) solutions are becoming more popular in mobile telecommunication systems to improve the portability and competitiveness of products. Since the analog/RF and digital blocks often share the same external power supply in SoC solutions, the on-chip generation of clean power supplies is necessary to avoid system performance degradation due to supply noises. Finally, the critical design issues for external capacitor-less low drop-out (LDO) regulators for SoC applications are addressed in this dissertation, especially the challenges related to power supply rejection at high frequencies as well as loop stability and transient response. The paths of the power supply noise to the LDO output were analyzed, and a power supply noise cancellation circuit was developed. The power supply rejection (PSR) performance was improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. Fabricated in a 0.18 ?m CMOS technology with 1.8 V supply, the entire proposed LDO consumes 55 ?A of quiescent current while in standby operation, and it has a drop-out voltage of 200 mV when providing 50 mA to the load. Its active core chip area is 0.14 mm2. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively.