Browsing by Subject "ADC"
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Item A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS(Texas A&M University, 2005-08-29) Stefanou, NikolaosHard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, fault-tolerant scheme to achieve high SFDR in an av- eraging flash A/D converter using comparator chopping. Chopping of comparators in a flash A/D converter was never previously implemented due to lack of feasibility in implementing multiple, uncorrelated, high speed random number generators. This work proposes a novel array of uncorrelated truly binary random number generators working at 1GHz to chop all comparators. Chopping randomizes the residual offset left after averaging, further pushing the dynamic range of the converter. This enables higher accuracy and lower bit-error rate for high speed disk-drive read channels. Power consumption and area are reduced because of the relaxed design requirements for the same linearity. The technique has been verified in Matlab simulations for a 6-bit 1Gsamples/s flash ADC under case of process gradients with non-zero mean offsets as high as 60mV and potentially serious spot offset errors as high as 1V for a 2V peak to peak input signal. The proposed technique exhibits an improvement of over 15dB compared to pure averaging flash converters for all cases. The circuit-level simulation results, for a 1V peak to peak input signal, demon- strate superior performance. The reported ADC was fabricated in TSMC 0.18 ??mCMOS process. It occupies 8.79mm2 and consumes about 400mW from 1.8V power supply at 1GHz. The targeted SFDR performance for the fabricated chip is at least 45dB for a 256MHz input sine wave, sampled at 1GHz, about 10dB improvement on the 6-bit flash ADCs in the literature.Item A 3-Bit Current Mode Quantizer for Continuous Time Delta Sigma Analog-to-Digital Converters(2012-02-14) Sundar, ArunThe summing amplifier and the quantizer form two of the most critical blocks in a continuous time delta sigma (CT ??) analog-to-digital converter (ADC). Most of the conventional CT ?? ADC designs incorporate a voltage summing amplifier and a voltage-mode quantizer. The high gain-bandwidth (GBW) requirement of the voltage summing amplifier increases the overall power consumption of the CT ?? ADC. In this work, a novel method of performing the operations of summing and quantization is proposed. A current-mode summing stage is proposed in the place of a voltage summing amplifier. The summed signal, which is available in current domain, is then quantized with a 3-bit current mode flash ADC. This current mode summing approach offers considerable power reduction of about 80% compared to conventional solutions [2]. The total static power consumption of the summing stage and the quantizer is 5.3mW. The circuits were designed in IBM 90nm process. The static and dynamic characteristics of the quantizer are analyzed. The impact of process and temperature variation and mismatch tolerance as well as the impact of jitter, in the presence of an out-of-band blocker signal, on the performance of the quantizer is also studied.Item A prototype of a new class of oversampling adc(Texas A&M University, 2006-08-16) He, JunAnalog-to-digital (A/D) and digital-to-analog (D/A) converters are important blocks in signal processing system because they provide the link between the analog world and digital systems. Compared with Nyquist-rate data converters, oversampling data converters are more desirable for modern submicron technologies with low voltage supplies. Today, all existing oversampling modulators in popular use are derived from sigma-delta modulation. Stability is the most significant problem in the sigma-delta modulator, because the ultimate accuracy is limited by stability. As the aggressiveness of the design increases, the margin of stability diminishes rapidly. This thesis presents the design and experimental results of the first prototype circuit implementation of the novel oversampling modulation scheme proposed by Dr. Takis Zourntos. This new class of oversampling modulators are theoretically stable. With less stability limitation, the new class of modulators can potentially achieve higher signal-to-noise ratio (SNR) or less power by designing the modulator more aggressively. This thesis describes the methods and procedures of how the new oversampling modulation theory is implemented into a circuit. Some novel circuit architectures are proposed in this modulator, such as a filter which can provide status outputs for the controller and realize arbitrary zeros and poles, comparators with synchronization latches to eliminate the effect of metastability, and a digital-to-analog converter (DAC) with current calibration circuits for high linearity. A third-order continuous-time oversampling modulator employing 4-bit quantization is implemented in a 0.35-??m double-poly complementary metal oxide semiconductor (CMOS) technology, with a chip area of 2150 ?? 2150 ??m2. Simulation results show it achieves 83.7-dB peak SQNR, 90-dB dynamic range over a 500kHz input signal bandwidth, and 60 mW power consumption.Item An attitude determination and control system for small satellites(2015-05) Tam, Margaret Hoi Ting; Fowler, Wallace T.; Lightsey, E. GlennA flexible, robust attitude determination and control (ADC) system is presented for small satellite platforms. Using commercial-off-the-shelf sensors, reaction wheels, and magnetorquers which fit within the 3U CubeSat form factor, the system delivers arc-minute pointing precision. The ADC system includes a multiplicative extended Kalman filter for attitude determination and a slew rate controller that acquires a view of the Sun for navigation purposes. A pointing system is developed that includes a choice of two pointing controllers -- a proportional derivative controller and a nonlinear sliding mode controller. This system can reorient the spacecraft to satisfy a variety of mission objectives, but it does not enforce attitude constraints. A constrained attitude guidance system that can enforce an arbitrary set of attitude constraints is then proposed as an improvement upon the unconstrained pointing system. The momentum stored by the reaction wheels is managed using magnetorquers to prevent wheel saturation. The system was thoroughly tested in realistic software- and hardware-in-the-loop simulations that included environmental disturbances, parameter uncertainty, actuator dynamics, and sensor bias and noise.Item Calibrated Continuous-Time Sigma-Delta Modulators(2010-07-14) Lu, Cho-YingTo provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.Item Circuit techniques for programmable broadband radio receivers(2013-12) Forbes, Travis Michael, 1986-; Gharpurey, RanjitThe functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF.Item Design of a time-based sigma-delta modulator(2010-08) Dutta, Arnab Kumar, 1984-; Hassibi, Arjang; Swanson, EricIn this thesis, a time-based oversampling sigma-delta analog-to-digital converter (ADC) architecture is introduced. This system uses time, instead of voltage, as the analog variable for it quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital pulse. The sigma-delta loop integrator, comparator, and subtractor are all time-based circuits and implemented by using only digital gates. The only voltage-based circuit is voltage-to-time Converter (VTC) which requires only a current source. No amplifier is required in the entire circuit. As a proof of concept, the simulation results for a prototype ADC incorporating this time-based sigma-delta ADC architecture is presented.Item Design of RF/IF analog to digital converters for software radio communication receivers(Texas A&M University, 2007-09-17) Thandri, Bharath KumarSoftware radio architecture can support multiple standards by performing analogto- digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 ?m SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ? 1.25 V supply. The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA architecture combines both cross coupling and source degeneration in order to obtain good IM3 performance. A system level digital tuning scheme is proposed to tune the ADC performance over process, voltage and temperature variations. The output bit stream of the ADC is captured using an external DSP, where a software tuning algorithm tunes the ADC parameters for best SNR performance. The IF ADC was designed in TSMC 0.35 ?m CMOS technology and it consumes 152 mW of power from ? 1.65 V supply.Item Design techniques for low-power SAR ADCs in nano-scale CMOS technologies(2016-05) Chen, Long; Sun, Nan; Viswanathan, T.R.; Pan, David Z.; Orshansky, Michael; Soenen, EricThis thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparator’s power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparator’s offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.Item High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications(2012-02-14) Zhang, HengThe prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5?10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.Item Integrated temperature sensors in deep sub-micron CMOS technologies(2014-05) Chowdhury, Golam Rasul; Hassibi, ArjangIntegrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.Item Investigation of 10-bit SAR ADC using flip-flip bypass circuit(2013-12) Fontaine, Robert Alexander; Sun, NanThe Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by settling time and control logic constraints. This report investigates a flip-flop bypass technique to reduce the required conversion time. A conventional design and flip-flop bypass design are simulated using a 0.18[micrometer] CMOS process. Background and design of the control logic, comparator, capacitive array, and switches for implementing the SAR ADCs is presented with the emphasis on optimizing for conversion speed.Item Low power VCO-based analog-to-digital conversion(2014-05) Gupta, Amit Kumar; Viswanathan, T. R., doctor of electrical engineering; Hassibi, Arjang; Touba, Nur; John, Lizy K; Sun, Nan; Nagaraj, KrishnaswamyThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Item Multichannel digital voltmeter using the LM3S8962 evaluation board(2016-08) Muckelroy, Callie Edward; Valvano, Jonathan W., 1953-; Bard, William Carl, 1944-This project is a proof of concept and prototype in both hardware and software, which demonstrates a useful and flexible 4-channel voltmeter using an LM3S8962 Evaluation Board, and commodity electronic components to serve as a shield circuit. The shield circuit protects the evaluation board from over/under voltage damage, and biases the incoming voltages to provide usable input voltages for the LM3S8962 ADC inputs. The report begins with an explanation of the goals of the project, and research of what current products exist on the commercial market to meet the needs of multichannel voltage measurement. In the interest of cost savings, and in the interest of an academic exploration of the capabilities of the inexpensive evaluation boards on the market, the author explores how the ADC inputs of the LM3S8962 can serve some of the same needs of much more expensive commercial products in voltage measurement. Several obstacles were encountered in the design and construction stages. A description of the obstacles, and how they were overcome is described. The end design of both the shield circuit and software is then detailed end-to-end, along with an explanation of how to use the end product. Finally, the accuracy of the project is assessed and demonstrated.Item System-level design and analysis of an embedded audio signal processing application(2016-05) Dollo, Philippe Marc; Sun, Nan; Akinwande, DejiIn this report, a design is proposed for an embedded system that implements an audio beamforming application. This design provides the key considerations for both the analog front-end, and the digital signal processing that would be included on-chip. The analog portion of the design implements a multi-order delta-sigma ADC, and the digital portion of the design implements a digital decimation filter and a beamforming filter. The objective of the project is to develop a system that could be used in a real-world implementation, with design decisions which attempt to account for system-wide specifications, rather than focusing on block-level performance alone.Item Tunable mismatch shaping for bandpass Delta-Sigma data converters(2011-05) Akram, Waqas; Swartzlander, Earl E.; Driga, Mircea D.; Orshansky, Michael E.; Telang, Vivek; Touba, Nur A.Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity.Item Ultra Low Power IEEE 802.15.4/ZIGBEE Compliant Transceiver(2011-02-22) Hussien, Faisal A.Low power wireless communications is the most demanding request among all wireless users. A battery life that can survive for years without being replaced, makes it realistic to implement many applications where the battery is unreachable (e.g. concrete walls) or expensive to change (e.g underground applications). IEEE 802.15.4/ZIGBEE standard is published to cover low power low cost applications, where the battery life can last for years, because of the 1% duty cycle of operation. A fully integrated 2.4GHz IEEE802.15.4 Compliant transceiver suitable for low power, low cost ZIGBEE applications is implemented. Direct conversion architecture is used in both Receiver and Transmitter, to achieve the minimum possible power and area. The chip is fabricated in a standard 0.18um CMOS technology. In the transmit mode, the transmitter chain (Modulator to PA) consumes 25mW, while in the receive mode, the iv receiver chain (LNA to Demodulator) consumes 5mW. The Integer-N Frequency Synthesizer consumes 8.5mW. Other Low power circuits are reported; A 13.56 Passive RFID tag and a low power ADC suitable for Built-In-Testing applications.Item VCO-based analog-to-digital conversion(2012-12) Hamilton, Joseph Garrett; Hassibi, Arjang; Viswanathan, T. R., doctor of electrical engineeringThis dissertation presents a novel [delta sigma] analog-to-digital converter architecture which replaces the operational amplifier-based integrator with a pair of tunable oscillators. A switched-capacitor V-I converter is used to combine the input voltage with a feedback DAC output and convert it into a current for two pseudo-differential current-controlled oscillators. The oscillator outputs are counted with a digital counter, and a digital back-end [delta sigma] modulator is used to truncate the high-resolution counter outputs for the feedback DAC path. This architecture has compelling advantages in deep sub-micron and emerging technologies where supply voltages are decreasing to a point that traditional analog architectures are no longer feasible. Additionally, this architecture takes advantage of the increased speed in these short-channel technologies. Measured results on a 6.08mW prototype in TSMC 0.18um achieving 63.5dB in a 2MHz bandwidth are presented.