Browsing by Author "Wu, Tung-Yeh"
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Item High speed 128-point Fast Fourier Transform circuit design for OFDM(2006-12) Wu, Tung-Yeh; Abraham, Jacob A.The Fast Fourier Transform (FFT) Algorithm is an efficient way to calculate the Discrete Fourier Transform, which is widely used in digital signal processing. Due to the increasing demand for Orthogonal Frequency Division Multiplexing (OFDM) wireless communication systems, it becomes even more important today. For the current Ultra Wide Band standard, the data sampling rate is 528 MHz. This thesis proposes a high-speed hardware FFT which targets next generation wireless communication systems with a 3.6 GHz sampling rate. This thesis is organized as follows. Chapter 1 introduces the motivation and the flow of the proposed design. Chapter 2 presents background knowledge of the Discrete Fourier Transform and the Fast Fourier Transform based on the Cooley- Tukey decomposition. It includes the basic theory and as well as the method to simplify the algorithm. Chapters 3 and 4 describe the design of the high speed arithmetic components for the FFT module. In Chapter 3, several high performance adders are implemented and compared. Chapter 4 discusses high speed multipliers. Implementation of a Dadda multiplier is also introduced. The conversion of the FFT from algorithm to hardware is explained in Chapter 5, which addresses several issues of concern as well as the tradeoffs between different approaches. Chapter 5 also presents the structure of the FFT and simulation results. Chapter 6 gives a summary of the work and points out the direction of future work.Item Power supply noise management : techniques for estimation, detection, and reduction(2010-12) Wu, Tung-Yeh; Abraham, Jacob A.; Gerosa, Gianfranco; Orshansky, Michael E.; Pan, David Z.; Yu, Shu-YiPower supply noise has become a critical issue for low power and high performance circuit design in recent years. The rapid scaling of the CMOS process has pushed the limit further and further in building low-cost and increasingly complex digital VLSI systems. Continued technology scaling has contributed to significant improvements in performance, increases in transistor density, and reductions in power consumption. However, smaller feature sizes, higher operation frequencies, and supply voltage reduction make current and future VLSI systems more vulnerable to power supply noise. Therefore, there is a strong demand for strategies to prevent problems caused by power supply noise. Design challenges exist in different design phases to reduce power supply noise. In terms of physical design, careful power distribution design is required, since it directly determines the quality of power stability and the timing integrity. In addition, power management, such as switching mode of the power gating technique, is another major challenge during the circuit design phase. A bad power gating switching strategy may draw an excessive rush current and slow down other active circuitry. After the circuit is implemented, another critical design challenge is to estimate power supply noise. Designers need to be aware of the voltage drop in order to enhance the power distribution network without wasting unnecessary design resources. However, estimating power supply noise is usually difficult, especially finding the circuit activity which induces the maximum supply noise. Blind search may be very time consuming and not effective. At post-silicon test, detecting power supply noise within a chip is also challenging. The visibility of supply noise is low since there is no trivial method to measure it. However, the supply noise measurement result on silicon is critical to debug and to characterize the chip. This dissertation focuses on novel circuit designs and design methodologies to prevent problems resulted from power supply noise in different design phases. First, a supply noise estimation methodology is developed. This methodology systematically searches the circuit activity inducing the maximum voltage drop. Meanwhile, once the circuit activity is found, it is validated through instruction execution. Therefore, the estimated voltage drop is a realistic estimation close to the real phenomenon. Simulation results show that this technique is able to find the circuit activity more efficiently and effectively compared to random simulation. Second, two on-chip power supply noise detectors are designed to improve the visibility of voltage drop during test phase. The first detector facilitates insertion of numerous detectors when there is a need for additional test points, such as a fine-grained power gating design or a circuit with multiple power domains. It focuses on minimizing the area consumption of the existing detector. This detector significantly reduces the area consumption compared to the conventional approach without losing accuracy due to the area minimization. The major goal of designing the second on-chip detector is to achieve self-calibration under process and temperature variations. Simulation and silicon measurement results demonstrate the capability of self-calibration regardless these variations. Lastly, a robust power gating reactivation technique is designed. This reactivation scheme utilizes the on-chip detector presented in this dissertation to monitor power supply noise in real time. It takes a dynamic approach to control the wakeup sequence according to the ambient voltage level. Simulation results demonstrate the ability to prevent the excessive voltage drop while the ambient active circuitry induces a high voltage drop during the wakeup phase. As a result, the fixed design resource, which is used to prevent the voltage emergency, can potentially be reduced by utilizing the dynamic reactivation scheme.