Browsing by Author "Farooqi, Aftab A."
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Item Low power test pattern generation for system on chip devices(2006-05) Farooqi, Aftab A.; Gale, Richard O.; Dallas, Timothy E. J.State of the art developments in the semiconductor manufacturing processes, integrated chip design methodology, availability of thousand plus pin integrated circuit (IC) packaging options and efficient IC test techniques have contributed immensely towards the integration of entire system on a chip. These System-On-Chip (SOC) devices can include multiple microprocessors, various types of memories such as SRAM, Flash and ROM, Digital Signal Processor(s), dozens of IP blocks and user defined logic. Various SOC test techniques have been innovated in the last decade to test complex mixed signal systems on a chip in a cost effective manner. The test industry has made great strides in developing new automated test equipment which can test logic, memory and analog components of the chip via external interface to the IC. Advances in the Built-In-Self-Test (BIST) techniques has enabled IC testing using a combination of external automated test equipment and BIST Controller on the chip. The power consumption of the chip during manufacturing test can be significantly higher than the power consumption of the chip in its target system. This increase in the power consumption can be attributed primarily to on-chip extremely random test pattern generation. This thesis probes into the various IC test approaches such as external, internal and embedded with specific investigation into the low power test stimulus generation. A new low power pattern generation technique is implemented. Conventional and low power test patterns are applied on an industry standard ISCAS-85 c432 27-channel interrupt controller circuit and average power consumption is measured. The results indicate 60% lower power consumption by the circuit using the new approach for an identical fault coverage of 98% in both cases.Item Low power test pattern generation for system on chip devices(Texas Tech University, 2006-05) Farooqi, Aftab A.State of the art developments in the semiconductor manufacturing processes, integrated chip design methodology, availability of thousand plus pin integrated circuit (IC) packaging options and efficient IC test techniques have contributed immensely towards the integration of entire system on a chip. These System-On-Chip (SOC) devices can include multiple microprocessors, various types of memories such as SRAM, Flash and ROM, Digital Signal Processor(s), dozens of IP blocks and user defined logic. Various SOC test techniques have been innovated in the last decade to test complex mixed signal systems on a chip in a cost effective manner. The test industry has made great strides in developing new automated test equipment which can test logic, memory and analog components of the chip via external interface to the IC. Advances in the Built-In-Self-Test (BIST) techniques has enabled IC testing using a combination of external automated test equipment and BIST Controller on the chip. The power consumption of the chip during manufacturing test can be significantly higher than the power consumption of the chip in its target system. This increase in the power consumption can be attributed primarily to on-chip extremely random test pattern generation. This thesis probes into the various IC test approaches such as external, internal and embedded with specific investigation into the low power test stimulus generation. A new low power pattern generation technique is implemented. Conventional and low power test patterns are applied on an industry standard ISCAS-85 c432 27-channel interrupt controller circuit and average power consumption is measured. The results indicate 60% lower power consumption by the circuit using the new approach for an identical fault coverage of 98% in both cases.Item MARKOV source based test length optimized scan built-in-self-test architecture(Texas Tech University, 2008-08) Farooqi, Aftab A.This dissertation presents several algorithmic and hardware design improvements to some of the recently proposed works using Markov sources for the scan built-in-test architecture. The first improvement is the use of the total probability rule and on-chip quantized probabilities to compute the sampling probability of the deterministic test cubes. Test cubes with low sampling probability are excluded from the final test set used to compute the transition probabilities. The second improvement is the use of new technique called dynamic transition selection, which combines transition inversion and transition fixing to produce test sequences. The third improvement is a new hardware design of the Markov source. Automatic Test Pattern Generator (ATPG) and fault simulator (HOPE) academic tools are used for generating deterministic test cubes and fault simulation, respectively. Espresso is used for logic minimization. The Sequential circiuit Synthesis tool (SIS) is used to map the synthesized design into a generic nand-nor library. Gate Equivalent (GE) count method [18] that reflects a static Complementary Metal Oxide Semiconductor (CMOS) technology: 0.5 GE for an inverter or a transmission multiplexer, (0.5)(n) GE’s for an n-input nand or nor, and (2.5)(n-1) GE’s for an n-input eXclusive-or (XOR) is used. The 5 larger International Symposium on Circuits and Systems (ISCAS89) benchmark circuits are tested using the new test pattern generator. The new test pattern generator achieves complete coverage of the stuck-at faults at signficantly reduced test length, with a modest increase in the gate count.