Pipelined sigma-delta modulators with interstage scaling
Chandrasekaran, Ramesh M.
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Sigma-Delta analog-to-digital converters (lA ADC) are capable of achieving high resolution ( > 15 bits) for moderate signal frequencies (<lOOlcHz). PipeUned converters are capable of handling high signal frequencies ( MHz ) at lower resolution. In this report, a new family of lA converters that utilize the noise shaping properties of ZA converters in conjunction with pipeHned architecture and interstage scaling is proposed, N bit quantizers, external to the ZA loop, provide a quantization error that is 1/2^ that of a single-bit quantizer. Pipelining M such stages with interstage scaling reduce the quantization error upto a factor of 1/2. Single-bit feedback lA modulators of any order L can be used to provide L-order noise shaping with the factor (1-z'^)^. The single-bit quantization error can thus be multiplied by a factor of (l-z'^)V2'^ This indicates that performance superior than either architecture is achieved by the proposed converter. Further, this concept of pipelining with interstage scaling can be extended to any unit lA modulator employing multibit internal quantizer. The implementation of a two-stage pipeline utilizing single-bit, first-order sigma-delta modulator and four-bit quantizers in silicon is described. Measurement results confirm the practicability of the proposed system.