Processing and reliability studies on hafnium oxide and hafnium silicate for the advanced gate dielectric application
MetadataShow full item record
As the CMOS integrated circuits reduce to the 100-nanometer regime and beyond, the conventional SiO2 based gate dielectric is facing serious challenges such as high leakage current, impurity diffusion, and dielectric thickness uniformity control across a 300 mm wafer. Consequently, high-k materials, which have higher dielectric constants (k) than SiO2, are expected to replace it as the gate insulator. Amongst all the materials investigated, HfO2 and its silicate appear to be the most promising candidates since they have thermodynamic stability in contact with silicon, reasonable energy bandgap (>5eV), moderate dielectric constant and good thermal expansion matching with Si. In this Ph.D. work, the issues with HfO2 and potential solutions to these problems are discussed. Since scaling of Hf-based high-k dielectrics has been limited due to the interfacial layer formation, NH3 surface nitridation has been investigated to reduce EOT and to improve reliability. Surface nitridation achieved a minimum EOT of 7.1Å, better thermal stability and higher breakdown field compared to a sample without surface nitridation. However, the surface nitridation exhibited adverse effects such as high hysteresis, lower interface quality and reduced carrier mobility. High-temperature forming gas (FG) prior to metallization successfully enhaced the carrier mobility of HfO2 gate dielectric MOSFETs with TaN gate electrode by improving HfO2/Si interface quality. Although improvement by high-temperature FG anneal was achieved, hydrogen atoms introduced by forming gas anneal can lead to unavoidable side effects such as poor NBTI and hot carrier degradation. Therefore, an attempt to reduce this degradation by using heavier deuterium atoms was executed. In addition to improved carrier mobility, improved reliability was also observed. Finally, the reliability issues of MOSFETs with hafnium silicate have been researched. A significant charge detrapping has been observed when the constant stress bias was removed. The rates of detrapping depend on the stress bias and time. Considering the fact that the real circuit operates at high frequency and low duty cycle, the reliability of high-k dielectric evaluated using conventional DC stress tests are excessively pessimistic to predict the long-term reliability of high-k gate dielectric. Polarity dependence of bias stress induced degradation was observed on the nMOSFET with HfSiON gate dielectric. Negative bias stress resulted in more significant increase of interface states and, accordingly, degradation of subthreshold swing than positive stress. It is suggested that the drain to gate stress on nMOSFET can damage the area of the high-k gate dielectric near the drain, resulting in asymmetric subthreshold swing degradation. Since this effect is more prominent in short channel MOSFETs, drain to gate stress during the off-state may play a greater role in the scaled devices.