Swartzlander, Earl E.709654912008-08-282017-05-112008-08-282017-05-112005http://hdl.handle.net/2152/2292textAbstract: A new phase-lock loop architecture is proposed to be used as a low-noise and high-frequency clock generation core for VLSI CMOS integration. The novel PLL architecture includes two charge pumps and an active loop filter architecture to implement a dual capacitance multiplication effect, which allows for the implementation of very large loop filter capacitors with very small silicon area. This new type of PLL is called a Clock Clean-up and Synthesis Unit (CCSU). The CCSU transient behavior was simulated with Simulink, and its noise performance was analyzed with MathCAD. The CCSU includes a novel one-stage oscillator with coarse and fine frequency tuning. The one-stage VCO is fairly insensitive to the Negative Bias Temperature Instability (NBTI) effect which affects p-channel MOS devices realized in deep submicron processes. The transistor level implementation of the proposed CCSU was implemented using and industrial strength 65 nm digital CMOS process using a single 1.0 V power supply.electronicengCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.Phase-locked loopsVoltage-controlled oscillatorsMetal oxide semiconductors, ComplementaryThesis