Duren, Russell Walker.Trower, John W.2013-05-152017-04-072013-05-152017-04-072012-122013-05-15http://hdl.handle.net/2104/8600Accelerating path planning algorithms with field programmable gate arrays (FPGA) allows the designer to achieve significant performance increases over using a traditional central processing unit (CPU). Converting an algorithm to run on an FPGA is a complicated and time consuming process. This thesis develops and verifies a design framework that demonstrates how to design a path planning algorithm in a high level language, then convert the algorithm into hardware description languages using high level synthesis tools. This design framework will be used to demonstrate the acceleration of a genetic algorithm.en-USBaylor University theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. Contact librarywebmaster@baylor.edu for inquiries about permission.Path planning algorithms.Field programmable gate arrays.FPGA.High level synthesis tools.Converting algorithms.ThesisWorldwide access.Access changed 5/21/14.