Touba, Nur A.2017-02-102018-01-222017-02-102018-01-222007-08http://hdl.handle.net/2152/45635This thesis describes a test pattern compression scheme that reduces test time by using specific on-chip decompression hardware for updating the test vector. Using the proposed hardware to update the test vector improves the bottleneck of data throughput between the tester and the device under test (DUT). This thesis uses an incrementor and an adder method to implement test decompression and compares the results. These approaches provide faster test times on a linear scale while retaining flexibility of test desired by industry.electronicengCopyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.Test pattern compression schemeChip decompression hardwareTest vectorThesisRestricted